ASIC Design Engineering Technical Lead (Hybrid)
Cisco
At a glance
AI generatedAs a Senior ASIC Design Engineer at Cisco Silicon One in San Jose, CA, you will join a specialized team focused on developing high-performance silicon for complex networks and data centers. Your role involves defining and designing front-end ownership of ASIC subsystems across various Cisco platforms, ensuring they meet stringent power, performance, and area goals. You will work closely with multi-disciplined engineering teams to implement complex developments using Verilog/SystemVerilog, driving technical execution from architecture through physical implementation. Responsibilities include leading design specifications, conducting technical reviews, collaborating on verification and integration challenges, mentoring engineers, and performing root-cause analysis for post-silicon validation issues. Essential skills include extensive ASIC design experience, expertise in high-performance RTL design, and knowledge of advanced technology nodes.
Skills
What you'll do
What we're looking for
Market check
This $165,000–$241,400 range sits above 61% of similar postings on FindRole.
Peer median band
$152,000–$221,800
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$154,525–$216,250
Middle half of comparable postings.
Based on 240 comparable postings.
* 240 is the maximum number of comparable postings sampled.
Employer
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has 113 open roles on FindRole.
Listed pay typically runs $165,000–$241,400 across 113 roles with salary data.
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