ASIC Design Engineer (Onsite)

Cisco

Actively hiring
Remote (Usa-San Jose, US) Posted 56 days ago $165,000$241,400 / year

At a glance

AI generated

TL;DR

As a Senior ASIC Design Engineer at Cisco Silicon One in San Jose, CA, you will join a specialized team focused on developing high-performance silicon for complex networks and data centers. Your role involves defining and designing front-end ownership of ASIC subsystems across various Cisco platforms, ensuring they meet stringent power, performance, and area goals. You will work closely with multi-disciplined engineering teams to implement complex developments using Verilog/SystemVerilog, driving technical execution from architecture through physical implementation. Responsibilities include leading design specifications, conducting technical reviews, collaborating on verification and integration challenges, mentoring engineers, and performing root-cause analysis for post-silicon validation issues. Essential skills include extensive ASIC design experience, expertise in high-performance RTL design, and knowledge of advanced technology nodes.

Skills

Verilog SystemVerilog RTL ASIC timing closure power optimization clock gating simulation synthesis static timing analysis Tape-out 2.5D fanout technologies high-performance silicon heterogeneous system integration

What you'll do

  • Define and design front-end ownership of ASIC subsystems for Cisco platforms.
  • Implement high-frequency, high-performance RTL in Verilog/SystemVerilog to meet strict targets.
  • Lead technical reviews and drive execution across architecture, verification, and physical implementation teams.
  • Collaborate with verification and physical design teams to resolve functional coverage and integration issues.
  • Mentor engineers and enhance engineering rigor and design quality within the team.

What we're looking for

  • Bachelor's degree in Electrical or Computer Engineering with 7+ years of ASIC design experience.
  • Master’s degree in Electrical or Computer Engineering with 4+ years of ASIC design experience.
  • Expertise in high-performance RTL design using Verilog/SystemVerilog.
  • Deep understanding of timing closure, power optimization, and clock gating techniques.
  • Experience with full ASIC development flows including simulation, synthesis, and static timing analysis.

Market check

Salary context

This $165,000–$241,400 range sits above 61% of similar postings on FindRole.

Peer median band

$152,000$221,800

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$154,525$216,250

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 113 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 113 roles with salary data.

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