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Active Keyword: ASIC Remove filter Location: Palo Alto Remove filter Clear all

12 of up to 20 (filtered)

Senior ASIC Design Engineer

SpaceX

Palo Alto, CA +3 18 days ago $175,000–$280,000
Actively hiring Confirmed live today Trusted Above market
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization
5+ yrs exp
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ASIC Design Engineer

SpaceX

Palo Alto, CA +2 18 days ago $135,000–$175,000
Actively hiring Confirmed live today Trusted Below market
ASIC Design FPGA Verilog SystemVerilog VHDL RTL Design Python C/C++ Bash SoC Integration DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer
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Senior ASIC Design Engineer

SpaceX

Irvine, CA +3 27 days ago $165,000–$265,000
Actively hiring Confirmed live yesterday Trusted Competitive pay
Verilog System Verilog RTL Design ASIC SoC Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization
5+ yrs exp
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Senior ASIC Design Engineer

SpaceX

Redmond, WA +3 27 days ago $165,000–$270,000
Actively hiring Confirmed live yesterday Trusted Above market
RTL Design Verilog System Verilog ASIC SoC Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems
5+ yrs exp
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Senior ASIC Design Engineer

SpaceX

Austin, TX +3 27 days ago
Actively hiring Confirmed live today Low trust
Verilog System Verilog RTL Design ASIC SoC Synthesis Timing Closure AXI AHB Python HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems Formality Check Silicon Bring-up
5+ yrs exp
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ASIC/SOC DFT Engineer

SpaceX

Austin, TX +1 82 days ago
Actively hiring Confirmed live today Low trust
ASIC DFT ATPG Verilog SystemVerilog Python Perl Bash UPF RTL Gate Level Simulation SDF DRC Formal Verification Synthesis Scan Insertion
1+ yrs exp
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ASIC/SOC DFT Engineer

SpaceX

Palo Alto, CA +1 82 days ago $135,000–$175,000
Actively hiring Confirmed live yesterday Low trust Below market
ASIC SOC DFT ATPG Verilog SystemVerilog Python Perl Bash csh UPF DRC RTL Gate Level Simulation SDF Formal Verification Synthesis Physical Design
1+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Palo Alto, CA 105 days ago $175,000–$280,000
Actively hiring Confirmed live today Low trust Above market
ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage
5+ yrs exp
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Senior ASIC DFT Engineer

SpaceX

Austin, TX +2 151 days ago
Actively hiring Confirmed live today Low trust
ASIC DFT Siemens Tessent ATPG Python Perl Tcl C++ ATE Post-Silicon Validation Gate-Level Simulation SDF IEEE 1500 IEEE 1149.1 BIST Scan Insertion Failure Analysis
5+ yrs exp
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Senior ASIC DFT Engineer

SpaceX

Irvine, CA +2 151 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
ASIC DFT Siemens Tessent ATPG Python Perl Tcl C++ Post-Silicon Validation ATE Teradyne Advantest SDF IEEE 1500 IEEE 1149.1 Scan Insertion BIST
5+ yrs exp
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Senior ASIC DFT Engineer

SpaceX

Palo Alto, CA +2 151 days ago $175,000–$280,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC DFT Siemens Tessent ATPG Python Perl Tcl C++ Post-Silicon Validation ATE Teradyne Advantest SDF Gate-Level Simulation IEEE 1500 IEEE 1149.1 BIST Scan Insertion
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Palo Alto, CA +3 154 days ago $175,000–$280,000
Actively hiring Confirmed live today Low trust Above market
ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
5+ yrs exp
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