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Active Keyword: IC Design Engineer Remove filter Location: Colorado Springs Remove filter Clear all

18 of up to 20 (filtered)

IC Design Engineer

Broadcom

Colorado Springs, CO +1 4 days ago $143,800–$230,000
Actively hiring Confirmed live yesterday Posted this week Trusted Competitive pay
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Asynchronous Clock Domain Crossing RAID Storage Designs Emulation Validation
10+ yrs exp
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IC Design Engineer

Broadcom

Colorado Springs, CO +1 4 days ago $143,800–$230,000
Actively hiring Confirmed live today Posted this week Trusted Competitive pay
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Asynchronous Clock Domain Crossing RAID Storage Designs Emulation Validation
10+ yrs exp
Save

IC Design Engineer

Broadcom

Colorado Springs, CO +1 4 days ago $143,800–$230,000
Actively hiring Confirmed live today Posted this week Trusted Competitive pay
Verilog SystemVerilog RTL Design Micro-architecture PCIe CXL AMBA Low-power Design Timing Closure RTL Optimization Asynchronous Clock Domain Crossing Multi-threaded Design Storage Designs Emulation Validation
10+ yrs exp
Save

IC Design Engineer

Broadcom

Colorado Springs, CO +1 4 days ago $143,800–$230,000
Actively hiring Confirmed live today Posted this week Trusted Competitive pay
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Asynchronous Clock Domain Crossing RAID Storage Designs Emulation Validation
10+ yrs exp
Save

RTL IC Design Engineer

Broadcom

Colorado Springs, CO +1 6 days ago $101,000–$162,000
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Emulation Validation RAID Storage
5+ yrs exp
Save

IC Design Engineer

Broadcom

Colorado Springs, CO +1 6 days ago $121,900–$195,000
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog SystemVerilog RTL Design Micro-architecture PCIe CXL AMBA Low-power Design Timing Closure RTL Optimization Asynchronous Clock Domain Crossing Multi-threaded Design Storage Designs Emulation Validation
8+ yrs exp
Save

IC Design Engineer

Broadcom

Colorado Springs, CO +1 6 days ago
Actively hiring Confirmed live today Posted this week High trust
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools Flow and Methodology Development
8+ yrs exp
Save

IC Design Engineer

Broadcom

Colorado Springs, CO +1 6 days ago $121,900–$195,000
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog SystemVerilog RTL Design Micro-architecture PCIe CXL AMBA Low-power Design Timing Closure RTL Optimization Asynchronous Clock Domain Crossing Multi-threaded Design RAID Storage Designs Emulation Validation
8+ yrs exp
Save

Physical Design Engineer

Broadcom

San Jose, CA +1 18 days ago
Actively hiring Confirmed live today Low trust
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools IC Design
10+ yrs exp
Save

Physical Design Engineer

Broadcom

San Jose, CA +1 18 days ago
Actively hiring Confirmed live today Low trust
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools IC Design
10+ yrs exp
Save

RTL IC Design Engineer

Broadcom

Colorado Springs, CO +1 19 days ago
Actively hiring Confirmed live today Low trust
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Emulation Validation RAID Storage Design Clock Domain Crossing
5+ yrs exp
Save

Physical Design Engineer

Broadcom

Colorado Springs, CO +1 29 days ago $121,900–$195,000
Actively hiring Confirmed live today Trusted Below market
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools IC Design
8+ yrs exp
Save

Physical Design Engineer

Broadcom

Colorado Springs, CO +1 29 days ago $129,400–$207,000
Actively hiring Confirmed live today Trusted Below market
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools IC Design
10+ yrs exp
Save

IC Design Engineer

Broadcom

Colorado Springs, CO +1 29 days ago $143,800–$230,000
Actively hiring Confirmed live today Trusted Competitive pay
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Asynchronous Clock Domain Crossing RAID Storage Designs Emulation Validation
10+ yrs exp
Save

Physical Design Engineer

Broadcom

Colorado Springs, CO +1 29 days ago $121,900–$195,000
Actively hiring Confirmed live today Trusted Below market
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools RTL
8+ yrs exp
Save

Physical Design Engineer

Broadcom

Colorado Springs, CO +1 29 days ago $129,400–$207,000
Actively hiring Confirmed live today Trusted Below market
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools RTL
10+ yrs exp
Save

Physical Design Engineer

Broadcom

Colorado Springs, CO +1 60 days ago $129,400–$207,000
Actively hiring Confirmed live today Low trust Below market
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools IC Design
10+ yrs exp
Save

Physical Design Engineer

Broadcom

Colorado Springs, CO +1 97 days ago
Actively hiring Confirmed live today Low trust
Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools IC Design
8+ yrs exp
Save