Physical Design Engineer

Broadcom

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Quick summary

Work type
On-site
Location
Colorado Springs, COSan Jose, CA
Employment
Full-time
Posted
75 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $205k
$138k most similar roles pay here $267k

This listing doesn't post a salary. Most similar roles pay $168,500–$241,750.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 224 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 161 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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The Physical Design Engineer joins the Data Center Solutions Group to support the development of PCIe Switch Products and Enterprise Storage Products. This role focuses on driving next-generation AI/ML ecosystems by managing the full physical design cycle from RTL to silicon tape-out. Daily responsibilities include performing synthesis, physical verification, and timing closure using various strategies, including top-level STA. The engineer will also execute floorplanning, layout, place and route, clock tree synthesis with skew balancing techniques, and EM/IR analysis while developing flows and methodologies. Collaboration with IC Design RTL Engineers is essential to ensure successful tape-outs. Required technical skills include proficiency in EDA tools and TCL or PERL scripting. Candidates must possess a bachelor’s degree in Electrical or Electronics Engineering and have at least eight years of relevant experience in the field.

What does a Physical Design Engineer earn in California?

Median $184362 from 32 postings across 9 companies.

See salary data

Skills

Physical Design Synthesis Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools RTL Tape-out

What you'll do

  • Execute the full physical design cycle from RTL to silicon tape-out.
  • Perform synthesis and timing closure using various methods and top-level STA strategies.
  • Conduct EM/IR analysis to ensure power integrity.
  • Execute Place and Route (P&R) processes for integrated circuits.
  • Perform Clock Tree Synthesis including custom clock trees, insertion reduction, and skew balancing.
  • Develop floorplans and layouts for complex IC designs.
  • Develop internal flows and methodologies for the physical design process.
  • Utilize TCL and PERL scripting to automate tasks and manage EDA tools.

What we're looking for

  • Bachelor's degree in Electrical Engineering or Electronics Engineering.
  • 8+ years of relevant experience.
  • Full physical design cycle experience from RTL to tape-out.
  • Proficiency in TCL and PERL scripting.
  • Proficiency in related EDA tools.
  • Experience in timing closure, including top-level STA (preferred).
  • Experience in floorplanning, specifically top-level floorplanning (preferred).
  • Excellent verbal and written communication skills.

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