IC Design Engineer

Broadcom

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Colorado Springs, COSan Jose, CA
Employment
Full-time
Posted
6 days ago
Freshness
Confirmed live today
Closes
Apr 18, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $196k
$140k $240k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $162,000–$229,650.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · IC Design Engineer

Role Posting Log in to save

The IC Design Engineer will join the Data Center Solutions Group to support the development of next generation AI/ML ecosystems through PCIe Switch Products and Enterprise Storage Products. This role requires in-depth expertise in all Physical Design aspects of taking RTL to silicon tape-out. Key responsibilities include executing Physical Design, Synthesis, Physical Verification, and Timing Closure. The engineer will perform RTL setup, EM/IR Analysis, Place and Route, Clock Tree Synthesis, and floor-planning. Candidates must demonstrate proficiency in TCL and PERL scripting along with related EDA tools. The position involves collaborating with IC Design RTL Engineers to manage flow and methodology development. The work focuses on solving complex technical challenges within high-performance data center infrastructure and storage hardware components.

Skills

Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools Flow and Methodology Development

What you'll do

  • Execute the full physical design cycle from RTL to silicon tape-out.
  • Perform synthesis, physical verification, and timing closure using various strategies.
  • Conduct top-level Static Timing Analysis (STA) and EM/IR analysis.
  • Manage floor-planning, layout, and place and route processes.
  • Perform Clock Tree Synthesis including custom clock trees and skew balancing.
  • Develop and maintain design flows and methodologies.
  • Write TCL and PERL scripts to automate design tasks.
  • Utilize industry-standard EDA tools to complete physical design tasks.

What we're looking for

  • Bachelor’s degree in Electrical Engineering or Electronics Engineering.
  • 8+ years of relevant experience.
  • In-depth knowledge of all Physical Design aspects from RTL to silicon tape-out.
  • Experience in Synthesis, Physical Verification, and Timing Closure.
  • Experience in EM/IR Analysis, Place and Route, and Clock Tree Synthesis.
  • Experience in Floor-planning and Layout (preferred: in-depth experience in top-level floorplanning).
  • Proficiency in TCL/PERL Scripting and related EDA Tools.
  • Excellent verbal and written communication skills.

Related searches

More IC Design Engineer jobs IC Design Engineer jobs in Colorado Springs All jobs at Broadcom

More like this

Similar roles

IC Design Engineer

Broadcom

Colorado Springs, CO +1 6 days ago $121,900–$195,000
Verilog SystemVerilog RTL Design Micro-architecture PCIe CXL AMBA Low-power Design Timing Closure RTL Optimization Asynchronous Clock Domain Crossing Multi-threaded Design RAID Storage Designs Emulation Validation
8+ yrs exp
Save

IC Design Engineer

Broadcom

Colorado Springs, CO +1 6 days ago $121,900–$195,000
Verilog SystemVerilog RTL Design Micro-architecture PCIe CXL AMBA Low-power Design Timing Closure RTL Optimization Asynchronous Clock Domain Crossing Multi-threaded Design Storage Designs Emulation Validation
8+ yrs exp
Save

IC Design Engineer

Broadcom

Colorado Springs, CO +1 29 days ago $143,800–$230,000
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Asynchronous Clock Domain Crossing RAID Storage Designs Emulation Validation
10+ yrs exp
Save

IC Design Engineer

Broadcom

Colorado Springs, CO +1 4 days ago $143,800–$230,000
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Asynchronous Clock Domain Crossing RAID Storage Designs Emulation Validation
10+ yrs exp
Save

IC Design Engineer

Broadcom

Colorado Springs, CO +1 4 days ago $143,800–$230,000
Verilog SystemVerilog RTL Design Micro-architecture PCIe CXL AMBA Low-power Design Timing Closure RTL Optimization Asynchronous Clock Domain Crossing Multi-threaded Design Storage Designs Emulation Validation
10+ yrs exp
Save

IC Design Engineer

Broadcom

Colorado Springs, CO +1 4 days ago $143,800–$230,000
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Asynchronous Clock Domain Crossing RAID Storage Designs Emulation Validation
10+ yrs exp
Save