Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: Timing Design Engineer Remove filter Location: Austin Remove filter Clear all

11 of up to 20 (filtered)

Senior Physical Design and Timing Engineer

Nvidia

Santa Clara, CA +3 28 days ago $136,000–$218,500
Actively hiring Confirmed live today Trusted Competitive pay
Physical Design Static Timing Analysis Logic Synthesis Floorplanning clock-tree synthesis Routing ECO RTL Python Tcl Perl Make AI ML DL LLMs EDA Tools Signoff IR Drop Xtalk
5+ yrs exp Hybrid
Save

GPU Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live yesterday Trusted
STA Timing Closure Physical Design RTL Synthesis DFT Clocking TCL Python Perl Shell Scripting ECO VLSI CMOS EDA Tools XALK POCVM ETMs
Save

Timing Design Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live today Trusted
STA ASIC Design Timing Closure Primetime SDC Tcl Perl Synthesis DFT Physical Design Signal Integrity RTL Timing Constraints
10+ yrs exp
Save

SoC Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live today Low trust
STA Timing Closure Physical Design ECO Perl TCL SPICE SoC OCV Crosstalk Circuit Modeling Netlist to Tapeout
Save

SoC Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live yesterday Low trust
STA Timing Closure Physical Design Perl TCL ECO SPICE SoC Netlist to Tapeout Circuit Modeling OCV Crosstalk
10+ yrs exp
Save

SoC Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live today Low trust
STA Timing Closure Physical Design Perl TCL ECO SPICE SoC Circuit Modeling OCV Crosstalk Netlist to Tapeout
3+ yrs exp
Save

CPU Physical Design Timing Engineer

Qualcomm

Austin, TX 40 days ago $129,500–$194,300
Actively hiring Confirmed live today High trust Below market
STA TCL Perl Python PrimeTime Tempus ICC2 Innovus RTL GDS Spice Signal Integrity Layout Parasitic Extraction CTS AOCV POCV
2+ yrs exp
Save

CPU Design Timing Engineer

Apple Inc

Austin, TX 59 days ago
Actively hiring Confirmed live yesterday Trusted
TCL Python Perl Primetime Tempus RTL Physical Design Place & Route Physically Aware Synthesis LEC DVS OCV Cross Talk Power Domains
Save

GPU Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 101 days ago
Actively hiring Confirmed live yesterday Low trust
STA Timing Closure Physical Design RTL Synthesis DFT Clocking TCL Python Perl Shell Scripting ECO VLSI CMOS EDA Tools Digital Logic Design Post Silicon Validation
Save

GPU Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 101 days ago
Actively hiring Confirmed live today Low trust
STA Timing Closure Physical Design TCL Python Perl Shell Scripting DFT Synthesis ECO EDA Tools RTL Clocking Post Silicon Validation Tapeout OCV Cross-talk
3+ yrs exp
Save

GPU Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 101 days ago
Actively hiring Confirmed live today Low trust
STA Timing Closure TCL Python Perl Shell Scripting EDA Tools RTL Synthesis DFT ECO Post Silicon Debug PPA OCV Cross-talk Clocking Physical Design
10+ yrs exp
Save