CPU Design Timing Engineer

As a CPU Design Timing Engineer, you will join the hardware team to manage all aspects of timing for high-performance CPU designs. Your daily responsibilities involve collaborating with micro-architects and implementation engineers to drive timing closure while working with the CAD team to develop, construct, and modify timing flows. You will write scripts to improve analysis flows and engineer efficiency using TCL, Perl, or Python. The role requires expertise in physical design tools and methodologies, including physically aware synthesis, place and route, extraction, and verification processes like LEC and DVS. You will address complex technical challenges such as managing multiple clock and power domains for 1 ghz+ designs while navigating crosstalk, noise, OCV, uncertainty, and derate methodology. Experience with static timing tools like Primetime or Tempus is highly preferred for this specialized role.