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Active Keyword: Timing Design Engineer Remove filter Clear all

20 of up to 20 (filtered)

Senior Physical Design and Timing Engineer

Nvidia

Westford, MA 7 days ago $168,000–$264,500
Actively hiring Confirmed live today Posted this week High trust Above market
Static Timing Analysis (STA) Synthesis ECO Physical Design RTL Python Tcl Make Synopsys PrimeTime Cadence Tempus Logical Equivalence Checking (LEC) DFT Floor-planning Routing Noise Analysis
8+ yrs exp
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Senior Physical Design and Timing Engineer

Nvidia

Santa Clara, CA +3 28 days ago $136,000–$218,500
Actively hiring Confirmed live today Trusted Competitive pay
Physical Design Static Timing Analysis Logic Synthesis Floorplanning clock-tree synthesis Routing ECO RTL Python Tcl Perl Make AI ML DL LLMs EDA Tools Signoff IR Drop Xtalk
5+ yrs exp Hybrid
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CPU Physical Design Timing Engineer

Qualcomm

Santa Clara, CA 34 days ago $209,300–$313,900
Actively hiring Confirmed live today High trust Above market
STA TCL Python Perl PrimeTime Tempus ICC2 Innovus RTL GDS Spice ASIC CTS AOCV POCV Signal Integrity Layout Parasitic Extraction
6+ yrs exp
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Physical Design and Timing Engineer Intern

Nvidia

Santa Clara, CA 35 days ago
Actively hiring Confirmed live today High trust
Physical Design Static Timing Analysis STA Power Analysis Logic Synthesis Equivalence Checking Placement Routing Python Perl Tcl Make Cadence Synopsys Siemens AI ML RTL GDSII
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CPU Server Physical Design Timing Engineer

Qualcomm

Santa Clara, CA 35 days ago $175,600–$263,400
Actively hiring Confirmed live today High trust Competitive pay
STA TCL Python Perl PrimeTime Tempus ICC2 Innovus RTL GDS Spice ASIC CTS AOCV POCV Signal Integrity Layout Parasitic Extraction
4+ yrs exp
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CPU Design Timing Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
Static Timing Analysis PrimeTime Tempus TCL Python Perl SDC RTL Logic Synthesis PnR Parasitic Extraction Logic Equivalence clock-domain crossing Assertion Based Verification CPU Microarchitecture
10+ yrs exp
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GPU Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live yesterday Trusted
STA Timing Closure Physical Design RTL Synthesis DFT Clocking TCL Python Perl Shell Scripting ECO VLSI CMOS EDA Tools XALK POCVM ETMs
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Timing Design Engineer

Apple Inc

Cupertino, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
STA ASIC Design Primetime Tcl Perl SDC Synthesis DFT Physical Design Timing Closure Signal Integrity RTL SoC Design
10+ yrs exp
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Timing Design Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live today Trusted
STA ASIC Design Timing Closure Primetime SDC Tcl Perl Synthesis DFT Physical Design Signal Integrity RTL Timing Constraints
10+ yrs exp
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Timing Design Engineer

Apple Inc

Waltham, MA 40 days ago $165,800–$292,400
Actively hiring Confirmed live yesterday Trusted Above market
STA ASIC Design Primetime SDC Tcl Perl Synthesis DFT Timing Closure Signal Integrity RTL SoC Design
10+ yrs exp
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Timing Design Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Trusted
STA ASIC Design Timing Closure Primetime SDC Tcl Perl Synthesis DFT Backend Signal Integrity RTL Clock Structure
10+ yrs exp
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Timing Design Engineer

Apple Inc

San Diego, CA 40 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
STA Timing Closure Primetime SDC Tcl Perl ASIC Design Synthesis DFT Physical Design Signal Integrity RTL Clock Structure
10+ yrs exp
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SoC Physical Design Engineer, STA/Timing

Apple Inc

San Jose, CA 40 days ago $129,300–$194,700
Actively hiring Confirmed live today Trusted Below market
STA Timing Closure Physical Design Perl TCL SPICE ECO SoC Circuit Modeling OCV Crosstalk
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SoC Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live today Low trust
STA Timing Closure Physical Design ECO Perl TCL SPICE SoC OCV Crosstalk Circuit Modeling Netlist to Tapeout
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SoC Physical Design Engineer, STA/Timing

Apple Inc

San Jose, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
STA Timing Closure Perl TCL Physical Design ECO SPICE SoC Circuit Modeling OCV Crosstalk Netlist to Tapeout
3+ yrs exp
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CPU Design Timing Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
Static Timing Analysis PrimeTime Tempus TCL Python Perl SDC RTL Logic Synthesis PnR Parasitic Extraction Logic Equivalence clock-domain crossing Assertion Based Verification CPU Microarchitecture
10+ yrs exp
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CPU Design Timing Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Trusted
Static Timing Analysis PrimeTime Tempus TCL Python Perl SDC RTL Logic Synthesis PnR Parasitic Extraction Logic Equivalence clock-domain crossing Assertion Based Verification Variation Modeling Noise Analysis
10+ yrs exp
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CPU Design Timing Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
Static Timing Analysis TCL Python Perl PrimeTime Tempus Logic Synthesis PnR Parasitic Extraction Logic Equivalence RTL CPU Microarchitecture Variation Modeling Noise Analysis Scripting
3+ yrs exp
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SoC Physical Design Engineer, STA/Timing

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live yesterday Low trust
STA Timing Closure TCL Python Perl Physical Design ECO SPICE OCV Crosstalk Circuit Modeling Netlist to Tapeout SoC Design
10+ yrs exp
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SoC Physical Design Engineer, STA/Timing

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live yesterday Low trust
STA Timing Closure Physical Design Perl TCL ECO SPICE SoC Circuit Modeling OCV Crosstalk Netlist to Tapeout
3+ yrs exp
Save