GPU Physical Design Engineer, STA/Timing

Apple Inc

Confirmed live yesterday Trusted

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Work type: On-site
Location: Austin, TX
Posted: 55 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $203k

$150k most similar roles pay here $253k

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

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TL;DR · GPU Physical Design Engineer, STA/Timing

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As a GPU Physical Design Engineer, STA/Timing within the Silicon Engineering group, you will be responsible for the timing closure of highly complex GPU designs. You will serve as a central point of contact for RTL and architecture teams to define physical design constraints while partnering with Synthesis and Physical Design teams to optimize for power, performance, and timing. Your daily responsibilities include setting up DFT modes, assembling top-level designs for STA, creating automation scripts, running ECO flows, and performing signoff checks for tapeout activities. You will utilize scripting languages like TCL, Python, Perl, and shell scripting while working with EDA tools and their APIs. The role focuses on solving technical challenges in high-performance processor design, specifically addressing timing convergence and ensuring high-quality silicon manufacture through advanced concepts such as XALK, POCVM, and ETMs.

Skills

STA Timing Closure Physical Design RTL Synthesis DFT Clocking TCL Python Perl Shell Scripting EDA Tools VLSI ECO CMOS Digital Logic Design

What you'll do

Coordinate with RTL and architecture teams to define physical design constraints for backend flows.
Partner with synthesis and physical design teams to optimize designs for power, performance, and timing.
Configure DFT modes and ensure all test features are properly timed.
Assemble top-level designs for STA by reviewing logs and reports to ensure accurate analysis.
Develop and maintain scripts and automation tools to improve the quality of STA reports.
Execute ECO flows to achieve final timing closure on complex GPU designs.
Perform a full suite of signoff checks to support tapeout activities and ensure high-quality silicon.
Collaborate with CAD teams and vendors to improve analysis flows and integrate new features.

What we're looking for

Bachelor's degree in Computer Science or Computer Engineering is required.
A Master's degree is preferred.
Experience or coursework in physical design, synthesis, DFT, or clocking is required.
Experience or coursework in digital logic design, RTL, DV, CMOS transistor logics, or VLSI concepts is required.
Proficiency with scripting languages such as TCL, Python, Perl, or shell scripting is required.
Internship or prior work experience in timing closure or physical design is preferred.
Experience working with EDA tools and exposure to their APIs is preferred.
Exposure to advanced concepts like XALK, POCVM, and ETMs is preferred.