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GPU Design Verification C++ Python SystemVerilog Verilog UVM Graphics Pipeline 3D Graphics Shaders Graphics APIs Formal Verification GPU Architecture +7 more Show less

SystemVerilog UVM C++ Python Perl GPU Design Verification Constrained-Random Testing Coverage-Driven Verification RTL Computer Architecture Hardware Modeling Emulation Performance Profiling Formal Verification +9 more Show less

Formal Verification SystemVerilog SystemVerilog Assertions (SVA) Python C/C++ Perl UVM Model Checking EDA Tools RTL Computer Architecture Graphics Pipelines UPF JIRA Confluence +10 more Show less

Verilog SystemVerilog RTL Design ASIC Design GPU Architecture Microarchitecture Synthesis Linting Timing Analysis SoC Hardware Design PPA Digital Design Cache Design Memory Systems Datapath Control Logic +12 more Show less

Cadence-Innovus TCL Python Physical Design Place and Route STA Power Gating Clock Gating floor planning Design for Yield +5 more Show less

PCB Design OrCAD Allegro SiWave Simplis PSpice HSpice Schematic Capture Analog Circuit Modeling Control Theory Closed Loop Compensation Stability Analysis Oscilloscope Function Generator PMIC SVIx +11 more Show less

C C++ Python Verilog SystemVerilog Perl Matlab Vulkan UVM RTL ASIC SoC DSP LTE 5G Wi-Fi Linux Windows Machine Learning +14 more Show less

STA Timing Closure Physical Design RTL Synthesis DFT Clocking TCL Python Perl Shell Scripting ECO VLSI CMOS EDA Tools XALK POCVM ETMs +13 more Show less

Physical Verification DRC ERC LVS Calibre P&R Flows Floorplanning ESD Design for Yield Manufacturability Multi Vt Strategies GPU Architecture Global Timing Verification Process ANT PERC +10 more Show less

ASIC Implementation Physical Design Place and Route Synthesis DFT Floorplanning PPA Optimization TCL Perl Python RTL Clock and Power Distribution Physical Signoff Design for Yield Thermal Management multi Vt +11 more Show less

ASIC Integration Physical Design Clock Distribution Floorplanning P&R Flows Timing Verification Netlist to Tapeout PPA ESD Solutions Design for Yield Manufacturability Multi Vt Strategies IP Integration +8 more Show less

DFT Design Verification Gate Level Simulation Python Perl TCL Object-Oriented Programming Coverage Analysis Assertions Pre-silicon Verification Logic Design GPU SoC Automation Scripts +9 more Show less

DFT Design Verification GPU SoC Gate Level Simulation Python Perl TCL Object-Oriented Programming Coverage Analysis Assertions Pre-silicon Verification Logic Design Automation Scripts +9 more Show less

DFT Design Verification Gate Level Simulation Python Perl TCL Object-Oriented Programming Coverage Analysis Assertions Pre-silicon Verification Silicon Bring-up Logic Design Test Benches Random Verification +9 more Show less

ASIC Integration Physical Design Floorplanning Place and Route Clock and Power Distribution Global Signal Planning I/O Planning Cadence Synopsys Timing Verification Physical Design Verification RTL Design for Yield Manufacturability multi Vt strategies ESD Solutions +11 more Show less

ASIC Integration Physical Design Floorplanning Place and Route Clock and Power Distribution Global Signal Planning I/O Planning Hard IP Integration Timing Verification Physical Design Verification RTL Design for Yield Multi Vt GPU Architecture +9 more Show less

Physical Design ASIC Implementation Place and Route Floorplanning Synthesis DFT Clock and Power Distribution RTL Multi-voltage Power Retention Design for Yield Manufacturability Thermal Management Tapeout +9 more Show less

System Verilog UVM OVM Universal Verification Methodology Python Ruby Perl VCS Verdi IES DVE HDL SIMD GPU Architecture Functional Coverage Waveform Viewers +11 more Show less

System Verilog C++ UVM OVM Python Ruby Perl VCS Verdi IES DVE HDL SIMD GPU Architecture Functional Coverage Waveform Viewers +11 more Show less

UVM OVM C++ Verilog Python Ruby Perl HDL SIMD Computer Architecture VCS Verdi IES DVE Functional Coverage Waveform Viewers +11 more Show less