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Logic Synthesis Verilog System Verilog RTL STA Python Perl Tcl UPF DFT ECO CAD Gate-level Netlist Lint ATPG +10 more Show less

Verilog RTL Design Cache Coherency Protocols Verdi Micro-architecture Gate-level Design LEC LEQ Clock Gating Power Gating Bus Gating Simulation Testbench Development +8 more Show less

Verilog System Verilog RTL SoC AHB AXI ARM RISCV Python C++ Perl Perforce GitHub STA Netlist +10 more Show less

Go TypeScript Rust Kafka Redis Kubernetes Terraform PostgreSQL SQL RESTful APIs gRPC DNS TLS/SSL HTTP Distributed Systems Cybersecurity Threat Modeling Agentic AI +13 more Show less

Video Conferencing Packet Capture Teams Azure AD Intune Active Directory Android Linux SIP TCP RTP HTTP HTTPS DNS USB Protocols VoIP System Log Analysis +12 more Show less

SQL Python ETL ELT Kafka RabbitMQ Tableau Tibco Spotfire Big Data Data Visualization Relational Databases +6 more Show less

Python Go Java Linux Kubernetes CI/CD Git DNS DHCP TCP/IP Routing Firewalls APIs Distributed Systems Cloud Computing SRE Infrastructure Automation Monitoring Observability +14 more Show less

SSPM CASB SaaS Security API Integration OAuth SSO SAML Scripting Automation Cloud Security Identity Security Risk Management +7 more Show less

VLSI RTL Python Perl Synthesis Static Timing Analysis Physical Design Boolean Optimization Netlist Validation HDL GPU Architecture Lint Checks Power Integrity Logic Design +9 more Show less

System Verilog Verilog RTL Synthesis Timing Closure Cadence Synopsys DFT Low Power Design Clock Gating Power Gating DVFS Netlist Generation SOC CAD Tools +10 more Show less

RTL-to-GDS Synthesis place-and-route PnR PPA Optimization Clock Flow CPU Microarchitecture Physical Design Memory Design +4 more Show less

Verilog System Verilog Python Perl Ruby RTL DFT UPF CPF CDC RDC STA Synthesis Invio LEC Genus Lint Simulation PPA Optimization SIMD Architecture +15 more Show less

Verilog System Verilog Python Perl Ruby RTL DFT LEC Lint Synthesis PPA Optimization Invio Genus SIMD Architecture Logic Design +10 more Show less

Verilog System Verilog RTL Logic Equivalence Checking Python Perl Ruby Synthesis PnR STA VLSI Design Digital Logic Design Computer Architecture SIMD DFT Invio +11 more Show less

RTL Synthesis Physical Design STA DFT UPF Python Tcl Perl Netlist Floor-planning Timing Analysis Gate-Level Simulation Logic Equivalence +10 more Show less

Verilog System Verilog Physical Synthesis PPA Optimization Static Timing Analysis STA DFT UPF RTL Gate-level Design Logic Equivalence Linting Tools Multi-clock Domain Multi-power Domain +9 more Show less

Verilog System Verilog Python Perl Ruby RTL DFT UPF CPF CDC RDC STA Synthesis Invio LEC Genus Lint Simulation PPA Optimization SIMD Architecture +15 more Show less

Verilog System Verilog Python Perl Ruby RTL LEC Lint Synthesis DFT PPA Optimization Invio Genus SIMD Architecture Logic Design +10 more Show less

RTL-to-GDS Synthesis place-and-route PnR PPA Optimization CPU Microarchitecture Clock Flow Physical Design Memory Design +4 more Show less

SystemVerilog RTL Design Python Perl Shell Scripting Logic Synthesis Static Timing Analysis Power Analysis Git Instruction Set Architecture Microarchitecture +6 more Show less