Graphics FE Integration Engineer

Apple Inc

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Work type
On-site
Location
Austin, TX
Posted
15 days ago
Freshness
Confirmed live today

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Similar $197k
$140k most similar roles pay here $251k

This listing doesn't post a salary. Most similar roles pay $162,000–$231,150.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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TL;DR · Graphics FE Integration Engineer

As a Graphics FE Integration Engineer within the Silicon Technologies group, you will join the GPU FE Design integration team to develop high-performance, power-efficient GPU technology. Your daily responsibilities involve creating GPU RTL by integrating various IPs while adhering to architectural parameters, physical constraints, DFT logic, and power intent. You will perform RTL integration, assembly, partitioning, transformation, and analysis while packaging and delivering front-end design collateral. The role requires debugging simulation failures, triaging logic equivalence issues, and ensuring implementation readiness through linting, custom checks, and synthesis. You will also author specification documents and collaborate with cross-functional teams. Required skills include proficiency in Verilog and SystemVerilog, along with experience in scripting languages like Perl, Ruby, or Python. Technical expertise includes PPA optimization, UPF/CPF power intent, CDC, RDC, and familiarity with GPU, CPU, and SIMD architectures.

What you'll do

  • Create GPU RTL by integrating various IPs following architectural parameters, physical constraints, and power intent.
  • Perform RTL integration tasks including assembly, partitioning, transformation, and analysis.
  • Package, qualify, and deliver front-end design collateral.
  • Debug simulation failures and triage logic equivalence failures between designs.
  • Ensure implementation readiness through linting, custom checks, synthesis, and clock/reset/power domain crossing checks.
  • Develop innovative methods to improve the front-end design integration process.
  • Author and sign off on design integration specification documents for customers and IP providers.

What we're looking for

  • Bachelor's degree and 10 years of experience.
  • Experience with Verilog or SystemVerilog.
  • Experience with Perl, Ruby, or Python.
  • Proficiency in logic design principles (preferred).
  • Ability to analyze architectural and micro-architectural details to drive design partitioning (preferred).
  • Knowledge of PPA optimization, Power Intent, CDC, RDC, synthesis, physical design, and STA (preferred).
  • Experience with RTL analysis and PPA optimization using Invio, LEC, and Genus (preferred).
  • Familiarity with GPU/CPU/SIMD architecture and micro-architecture (preferred).

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