FE Engineering

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $182k

$124k most similar roles pay here $229k

This listing doesn't post a salary. Most similar roles pay $144,400–$219,131.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · FE Engineering

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FE Engineering joins the Apple Graphics team to manage logic synthesis for GFX partitions. The role involves performing synthesis, analysis, and optimization of delivered IP while collaborating with RTL and physical design teams to meet demanding power, performance, and area targets. Daily responsibilities include running synthesis trials in industry tools, ensuring designs are lint clean and logically equivalent, and managing DFT chain insertion for test coverage. You will also perform ECOs to address netlist changes post-release and conduct signoff checks. Technical requirements include experience with Verilog or SystemVerilog, static timing analysis, and Unified Power Format specifications. To automate design flows and reporting tasks, you must be proficient in scripting languages such as Python, Perl, or Tcl. The role focuses on optimizing digital circuit designs to achieve high-quality results for silicon production.

Skills

Logic Synthesis Verilog System Verilog RTL STA Python Perl Tcl UPF DFT ECO CAD Gate-level Netlist Lint ATPG

What you'll do

Perform logic synthesis for GFX partitions to optimize power, performance, and area (PPA) metrics.
Ensure designs are logically equivalent, lint clean, and meet all DFT requirements.
Analyze and debug digital logic at the Register Transfer Level (RTL) using Verilog or SystemVerilog.
Conduct formal logic equivalence verification between RTL and gate-level netlists.
Perform static timing analysis (STA) to identify and resolve timing violations on critical paths.
Develop Python, Perl, or Tcl scripts to automate design flows and reporting tasks.
Implement and verify Engineering Change Orders (ECOs) at the gate-level netlist post-release.
Analyze designs incorporating multiple power domains defined by Unified Power Format (UPF) specifications.

What we're looking for

Master's degree or foreign equivalent in Electrical Engineering or a related field.
At least 1 year of experience in the job offered or a related occupation.
Experience performing physical synthesis to optimize digital circuit designs for power, performance, and area (PPA) trade-offs.
Experience analyzing and debugging digital logic in Hardware Description Languages like Verilog or SystemVerilog at the RTL level.
Experience performing formal logic equivalence verification between Register Transfer Level (RTL) and gate-level netlists.
Experience performing static timing analysis (STA) to identify and debug timing violations on critical paths.
Experience developing scripts using Python, Perl, or Tcl to automate design flows, data extraction, and reporting tasks.
Experience implementing and verifying functional and timing Engineering Change Orders (ECOs) at the gate-level netlist.

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