FE Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Austin, TX
Posted
16 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $177k
$126k most similar roles pay here $229k

This listing doesn't post a salary. Most similar roles pay $139,875–$214,000.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · FE Engineer

Role Posting Log in to save

As a FE Engineer, you will join the hardware team to integrate internal and external intellectual property by designing system bus and control bus logic for connectivity of IP blocks to the main SOC infrastructure. You will own the integration specification for design projects while integrating and optimizing memories and hard macros. Daily responsibilities include running synthesis, netlist generation, and timing closure while collaborating with architecture, verification, physical design, DFT, and power teams to ensure first tape out success. You will develop and maintain methodology flows and checks to ensure high-quality delivery. Required skills include using System Verilog or Verilog for RTL, managing multiple clock and reset domains, and applying low power concepts like clock gating and DVFS. You must also utilize Synopsys or Cadence synthesis tools and CAD tools to ensure design quality.

Skills

System Verilog Verilog RTL Synthesis Timing Closure Cadence Synopsys DFT Low Power Design Clock Gating Power Gating DVFS Netlist Generation SOC CAD Tools

What you'll do

  • Integrate internal and external IP by designing system bus and control bus logic for SoC connectivity.
  • Own the Integration Spec for the assigned design project.
  • Integrate and optimize memories and hard macros required for the block.
  • Perform synthesis, netlist generation, and timing closure for the block.
  • Develop and maintain methodology, flows, and checks for owned designs.
  • Implement low power design concepts such as clock gating, power gating, and DVFS.
  • Incorporate Design-for-test (DFT) concepts to support scan insertion for overall testability.

What we're looking for

  • Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
  • Experience or education in using System Verilog or Verilog to write RTL for integration components.
  • Experience managing multiple clock domains and reset domains while applying techniques to resolve associated issues.
  • Experience utilizing low power design concepts such as clock gating, power gating, and DVFS to meet targets.
  • Experience using Synopsys or Cadence synthesis tools to apply timing constraints and synthesize designs.
  • Experience integrating RTL components into sub-systems that interface with memories.
  • Experience utilizing Design-for-test concepts to support scan insertion for overall testability.
  • Experience utilizing CAD tools to ensure the quality of design.

Related searches

More FE Engineer jobs FE Engineer jobs in Austin All jobs at Apple Inc

More like this

Similar roles

FE Engineer

Apple Inc

Cupertino, CA 2 days ago $150,400–$225,300
System Verilog Verilog RTL Python Perl TCL Cadence Synopsys Computer Architecture Digital Logic Design Assertion Methodology Power Closure Synthesis Physical Verification Signal Integrity Cache Coherence
Save

FE Engineer

Apple Inc

Cupertino, CA 2 days ago $174,149–$225,300
System Verilog VHDL Verilog RTL TCL Python Perl Linux Unix Synopsys Design Compiler Cadence Genus DFT CDC Lint Logic Synthesis Timing Analysis PPA Optimization Netlist Generation
Save

FE Engineer

Apple Inc

Austin, TX 2 days ago
Verilog System Verilog RTL SoC AHB AXI ARM RISCV Python C++ Perl Perforce GitHub STA Netlist
2+ yrs exp
Save

FE Engineer

Apple Inc

Austin, TX 2 days ago
Verilog RTL Design Cache Coherency Protocols Verdi Micro-architecture Gate-level Design LEC LEQ Clock Gating Power Gating Bus Gating Simulation Testbench Development
Save

FE Engineer

Apple Inc

Austin, TX 31 days ago
Python Perl TCL Innovus ICC Tempus Primetime Synopsys Cadence Mentor RTL PPA Low Power Design Data Analysis Visualization Semiconductor Design Physical Design Timing Closure
3+ yrs exp
Save

FE Engineer

Apple Inc

Cupertino, CA 2 days ago $174,149–$225,300
System Verilog Verilog RTL Python Perl TCL CDC RDC UPF CPF Synopsys Cadence LEC LEQ SoC DVFS Synthesis
Save