Front End Engineering

What you'll do

• Implement designs for chips in hardware devices by converting RTL code into digital logic gates.
• Perform static timing analysis and develop constraints to ensure physical designs meet timing requirements.
• Conduct power integrity checks to verify that various power domains and interfaces are complete.
• Develop and maintain signoff flows to verify the overall quality of chip designs.
• Implement Engineering Change Orders (ECOs) to achieve functionality and timing closure.
• Collaborate with CAD teams and tool vendors to resolve flow or integration issues.
• Create innovative flows and processes to support new chip designs.
• Optimize logic designs to achieve goals for low power, small area, and high performance.

What we're looking for

• Master's degree or foreign equivalent in Electrical & Computer Engineering or a related field.
• At least 2 years of experience in the job offered or a related occupation.
• Experience using VLSI design and timing to evaluate engineering tradeoffs.
• Knowledge of HDL to understand design functionality and suggest improvements.
• Proficiency in Perl and Python for task automation.
• Experience using physical design concepts to improve timing, reduce congestion, and implement ECOs.
• Experience using synthesis techniques and Boolean optimization to recover area, power, and fix timing violations.
• Experience using simulation and debugging tools for RTL and Netlist validation.