FE Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Austin, TX
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $177k

$126k most similar roles pay here $229k

This listing doesn't post a salary. Most similar roles pay $139,875–$214,000.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · FE Engineer

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As an FE Engineer, you will join the hardware team to collaborate with architects in defining design microarchitecture hierarchies and developing detailed specifications. Your daily responsibilities involve owning all aspects of RTL development for specific blocks based on established guidelines, integrating shared IP blocks, and optimizing memories and hard macros. You will work closely with front-end synthesis, STA, power, performance, and functional verification teams to ensure high quality and timely delivery through rigorous checks. The role requires proficiency in Verilog and SystemVerilog for designing subsystems that meet power, performance, and area targets. You will utilize C++, Python, or Perl for automation, manage code via Perforce or GitHub, and implement protocols like AHB/AXI and architectures such as ARM/RISCV. Additionally, you will perform gate-level netlist edits and analyze timing reports to resolve functional and timing issues.

Skills

Verilog System Verilog RTL SoC AHB AXI ARM RISCV Python C++ Perl Perforce GitHub STA Netlist

What you'll do

Define microarchitecture hierarchies and interfaces based on SoC architecture requirements.
Develop RTL designs for blocks using Verilog or SystemVerilog to meet power, performance, and area targets.
Integrate common and shared IP blocks while optimizing memories and hard macros.
Collaborate with synthesis and STA teams to ensure all timing requirements are met.
Implement industry standard interconnect protocols such as AHB/AXI and CPU architectures like ARM/RISC-V.
Analyze gate-level netlists to perform logical transformations for fixing functional bugs.
Analyze timing reports and implement RTL logic changes to resolve timing issues.
Perform design optimizations to minimize static and dynamic power consumption within the subsystem.

What we're looking for

Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field.
At least 2 years of experience in the job offered or a related occupation.
Experience translating SoC architecture requirements into microarchitecture specifications for subsystem blocks.
Proficiency in Verilog and System Verilog to design subsystems meeting power, performance, and area targets.
Ability to use programming or scripting languages such as C++, Python, or Perl to automate design development.
Experience defining verification requirements for designed subsystems to ensure design correctness.
Knowledge of industry standard SoC interconnect protocols (AHB/AXI), CPU architectures (ARM/RISC-V), and peripherals.
Ability to use source code management tools like Perforce or GitHub, analyze timing reports, and optimize for power consumption.

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