RTL Feasibility Engineer, AI/ML Processors

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$101,400–$152,200 / yr
Posted
17 days ago
Freshness
Confirmed live yesterday
Closes
Mar 16, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $215k
This role $127k
$80k most similar roles pay here $299k

This role pays less than 98% of similar roles. Most pay $187,850–$241,750 — the shaded band above. At the midpoint, this role pays about $127k versus about $215k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 564 open roles on FindRole.

Listed pay typically runs $152,800–$222,500 across 545 roles with salary data.

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At a glance

TL;DR · RTL Feasibility Engineer, AI/ML Processors

As an RTL Feasibility Engineer, AI/ML Processors, you will join the AI/ML processor logic design team to support the microarchitecture and logic design development of state-of-the-art processors used across various applications. You will work closely with architects and designers to provide critical feedback on power, timing, and area feasibility for specific design features. Your daily responsibilities include performing logic synthesis, early static timing analysis, and early power analysis before the full implementation cycle begins. You will evaluate every stage of the design process from instruction set architecture to final implementation while troubleshooting issues with tools and flows. The role requires proficiency in SystemVerilog, RTL design concepts, and scripting languages including Python, Perl, and Shell. Additionally, you must be skilled in using digital design simulators, synthesis engines, power estimation tools, and Git revision control systems.

What you'll do

  • Perform microarchitecture and logic design development for state-of-the-art AI/ML processors.
  • Provide feedback on power, timing, and area (PPA) feasibility for various design features.
  • Execute logic synthesis, early static timing analysis, and early power analysis before full implementation.
  • Evaluate the entire design process from instruction set architecture to final implementation.
  • Utilize system tools including digital design simulators, synthesis engines, and power estimation engines.
  • Troubleshoot and resolve technical issues with internal tools and workflows.
  • Develop scripts using Python, Perl, and Shell for automation and design tasks.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field.
  • Strong scripting skills in Python, Perl, and Shell scripting.
  • Familiarity with SystemVerilog and RTL design concepts.
  • Experience with Git and other revision control systems.
  • Excellent communication and collaboration skills.
  • Ability to work independently and in a team-oriented environment.

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