Graphics FE Implementation Engineer

Apple Inc

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Work type: On-site
Location: Austin, TX
Posted: 15 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Similar $207k

$137k most similar roles pay here $277k

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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TL;DR · Graphics FE Implementation Engineer

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As a Graphics FE Implementation Engineer, you will join the GPU FE Implementation team to optimize and deliver world-class GPUs into Apple Silicon. You will be responsible for PPA optimization of the netlist while collaborating closely with RTL and Physical design teams to meet key netlist quality milestones for your specific partition. Your daily work involves improving current methodologies and ensuring high-quality designs for consumer products. The role requires proficiency in physical synthesis, logic and PPA optimization techniques, and experience with Verilog or SystemVerilog scripting languages. You will utilize logic equivalence tools for RTL and Gate-level designs while applying principles of static timing analysis and critical path analysis. Additional technical competencies include familiarity with DFT insertion, multi-clock/power domains, linting tools, and implementing ECOs for functionality and timing across various hardware components.

Skills

Verilog System Verilog Physical Synthesis PPA Optimization Static Timing Analysis STA DFT UPF RTL Gate-level Design Logic Equivalence Linting Tools Multi-clock Domain Multi-power Domain

What you'll do

Perform PPA optimization of the netlist in coordination with RTL and Physical design teams.
Deliver key netlist quality milestones for assigned partitions.
Improve and refine existing engineering methodologies for GPU implementation.
Analyze critical paths to guide RTL designs toward optimal solutions.
Implement ECOs for both functionality and timing requirements.
Utilize logic equivalence tools for RTL and Gate-level designs.
Manage complex design constraints including multi-clock, multi-power domains, and DFT insertion.

What we're looking for

Bachelor of Science degree and 3 years of relevant experience.
Experience with physical synthesis, including logic and PPA optimization techniques.
Experience with Verilog, SystemVerilog, or other scripting languages.
Experience using logic equivalence tools for RTL and Gate-level designs.
Understanding and application of physical design (PD) and static timing analysis (STA) principles (preferred).
Ability to analyze critical paths and guide RTL designs to optimal solutions (preferred).
Familiarity with DFT insertion, linting tools, and multi-domain concepts (preferred).
Experience implementing ECOs for functionality and timing (preferred).

Similar roles

Graphics FE Implementation Engineer

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Santa Clara, CA 15 days ago $129,300–$194,700

RTL System Verilog Verilog Python Tcl Perl Synthesis Static Timing Analysis DFT CDC ECO CMOS VLSI Digital Logic Design Netlist Generation Place and Route

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