FE Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $177k

$126k most similar roles pay here $229k

This listing doesn't post a salary. Most similar roles pay $139,875–$214,000.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · FE Engineer

Role Posting Log in to save

The FE Engineer joins the hardware team to execute development, assessment, and refinement of RTL design to meet specific power, performance, area, and timing goals. This role involves supporting testbench development and simulation for functional and performance verification while exploring high performance strategies to validate that RTL designs meet targets. Working with a multi-functional engineering team, the individual will implement and validate physical designs. Key responsibilities include performing high-level micro-architecture, designing new features for chip improvement, and analyzing timing paths using industry standard tools. The role requires proficiency in Verilog for core IPs, complex FSMs, cache coherency protocols, and advanced hardware prefetching techniques. Candidates must utilize debugging tools like Verdi, perform ECOs with LEC/LEQ tools, and implement low power design concepts such as clock gating, power gating, and bus gating to optimize the chip.

Skills

Verilog RTL Design Cache Coherency Protocols Verdi Micro-architecture Gate-level Design LEC LEQ Clock Gating Power Gating Bus Gating Simulation Testbench Development

What you'll do

Develop and refine RTL designs to meet specific power, performance, area, and timing goals.
Write Verilog code for core IPs including complex FSMs and power-saving features.
Implement cache coherency protocols and advanced hardware prefetching techniques.
Support testbench development and simulation for functional and performance verification.
Perform high-level micro-architecture design to improve chip performance and timing.
Analyze timing paths using industry standard tools and perform ECOs using LEC/LEQ tools.
Implement low power design features such as clock, power, and bus gating.
Use debugging tools like Verdi and architecture models for daily RTL code maintenance.

What we're looking for

Bachelor's Degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field.
Experience or education in using Verilog to write RTL for core IPs.
Experience performing RTL design with complex FSMs and power savings features.
Experience using cache coherency protocols and interfaces.
Experience using advanced hardware prefetching techniques and algorithms.
Proficiency in utilizing debugging tools like Verdi and architecture models for RTL code maintenance.
Ability to perform high-level micro-architecture, including designing new features for performance, power, and timing.
Expertise in analyzing timing paths with industry standard tools and understanding gate-level design.

Similar roles

FE Engineer

Apple Inc

Austin, TX 2 days ago

Verilog System Verilog RTL SoC AHB AXI ARM RISCV Python C++ Perl Perforce GitHub STA Netlist

2+ yrs exp

Save

FE Engineer

Apple Inc

Austin, TX 16 days ago

System Verilog Verilog RTL Synthesis Timing Closure Cadence Synopsys DFT Low Power Design Clock Gating Power Gating DVFS Netlist Generation SOC CAD Tools

Save

FE Engineer

Apple Inc

Austin, TX 31 days ago

Python Perl TCL Innovus ICC Tempus Primetime Synopsys Cadence Mentor RTL PPA Low Power Design Data Analysis Visualization Semiconductor Design Physical Design Timing Closure

3+ yrs exp

Save

FE Engineer

Apple Inc

Cupertino, CA 2 days ago $174,149–$225,300

System Verilog Verilog RTL Python Perl TCL CDC RDC UPF CPF Synopsys Cadence LEC LEQ SoC DVFS Synthesis

Save

FE Engineer

Apple Inc

Cupertino, CA 2 days ago $150,400–$225,300

System Verilog Verilog RTL Python Perl TCL Cadence Synopsys Computer Architecture Digital Logic Design Assertion Methodology Power Closure Synthesis Physical Verification Signal Integrity Cache Coherence

Save

FE Engineer

Apple Inc

Cupertino, CA 2 days ago $174,149–$225,300

System Verilog VHDL Verilog RTL TCL Python Perl Linux Unix Synopsys Design Compiler Cadence Genus DFT CDC Lint Logic Synthesis Timing Analysis PPA Optimization Netlist Generation

Save