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x86 Architecture Post-Silicon Validation System-Level Debug Firmware BIOS Linux C C++ Python PCIe Memory Power Management RAS Virtualization High-Speed I/O SoC Automation Validation Methodologies +13 more Show less

Verilog SystemVerilog RTL Design CPU Architecture ASIC Logic Design Synthesis Timing Closure Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Cache Hierarchy TLB Branch Prediction +12 more Show less

SoC Architecture C++ C Python Perl Performance Modeling RTL SIMD Prefetching Data Structures Algorithms Workload Analysis Performance Simulation +8 more Show less

SoC Architecture C++ C Python Perl Performance Modeling RTL SIMD Prefetching Data Structures Algorithms Workload Analysis MP Performance +8 more Show less

CPU Microarchitecture Performance Modeling Cycle-accurate Simulators C++ Python Workload Analysis Performance Profiling power, and area trade-offs Software Engineering Practices +4 more Show less

CPU Physical Design DTCO Synthesis Place-and-Route Static Timing Analysis PPA Python Tcl Perl timing-closure Silicon Design AI Tools Hardware Design Pathfinding +9 more Show less

SoC Architecture C++ C Python Perl Performance Modeling RTL SIMD Prefetching Data Structures Algorithms Workload Analysis MP Performance +8 more Show less

CPU Architecture Micro-architecture C C++ Python Perl Javascript SoC ML Performance Analysis Compiler Technology OS Internals Data Analysis Simulators +9 more Show less

CPU Architecture Micro-architecture C C++ Python Perl JavaScript SoC ML AR/VR Performance Analysis Compiler Technology OS Internals Data Analysis Frameworks Simulation +10 more Show less

CPU Architecture RTL Physical Design VLSI Circuit Design Power Delivery Power Gating Thermal Throttling Advanced Packaging SoC Design Process Technology High-Frequency Design Power Management +8 more Show less

Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Static Timing Analysis Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Timing Closure +11 more Show less

CPU Architecture Micro-architecture C++ Python Perl RTL SIMD Vector Architectures Compiler Technologies OS Internals Data Structures Algorithms Software Design Patterns Branch Prediction Prefetchers Power Efficiency +11 more Show less

CPU Architecture Micro-architecture C C++ Python Perl SIMD Vector Architectures RTL Data Structures Algorithms Software Design Patterns OS Internals Compiler Technologies Branch Prediction Prefetchers +11 more Show less

CPU Architecture Micro-architecture C C++ Python Perl SIMD Vector Architectures RTL Data Structures Algorithms Software Design Patterns OS Internals Compiler Technologies Branch Prediction Prefetchers CPU Pipelines +12 more Show less

Tcl Python Cadence Innovus Place-and-Route Physical Design Timing Analysis Physical Verification Digital Design Automation PPA 5nm Hardware Engineering +7 more Show less

RTL Synthesis place-and-route Static Timing Analysis STA floor-planning PPA DRC LVS ECO Power Intent Validation IR Drop EMIR +8 more Show less

Static Timing Analysis (STA) Python Tcl CI/CD ECO Synthesis PnR Test Driven Development AI +4 more Show less

CPU Architecture C C++ Python Perl RTL SIMD micro-architecture Performance Modeling OS Internals Compiler Technology Post-silicon Verification Benchmarks +8 more Show less

RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution +7 more Show less

CPU Architecture C C++ Python Perl RTL SIMD MMU Cache Compiler Technology OS Internals Performance Modeling Benchmarks Post-Silicon Verification +9 more Show less