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Synthesis STA TCL Formal Verification DC Genus Fusion Compiler CLP Timing Analysis FPGA DSP Hardware Engineering +7 more Show less

CPU Design Micro-architecture Logic Design C C++ Python Perl Verilog VHDL Synthesis Design Verification Simulation Emulation Formal Verification Silicon Validation Computer Architecture Physical Design +12 more Show less

C C++ Python ARMv8 ARMv9 RISCV Assembly Linux RTOS Zephyr RTOS Firmware Unit Testing Code Review Hardware-Software Co-design +9 more Show less

Agentic AI AI Inference RAG Speculative Decode Vector Databases Model Serving CPU Datacenter Platforms Cloud Infrastructure Benchmarking Performance Optimization +6 more Show less

STA PrimeTime Tempus ICC2 Innovus TCL Python Perl RTL GDS Spice Signal Integrity Layout Parasitic Extraction ASIC Back-end Design CTS POCV AOCV +12 more Show less

LSF Build Systems CI/CD Verilog SystemVerilog C++ Perl Semiconductor Design Artifact Management Compute Farm Scheduling +5 more Show less

RTL Verilog CPU Architecture Microarchitecture ASIC SoC x86 ARM Synthesis static timing *analysis DFT DFD Power Management Perl Shell Tcl Floorplan Tapeout +13 more Show less

RTL SystemVerilog Microarchitecture CPU Design Silicon Debug Timing Closure Power Optimization DFT CAD Emulation Physical Design SIMD Memory Hierarchy Low-power Design AI-assisted design workflows +10 more Show less

Static Timing Analysis Python Tcl CI/CD Synthesis PnR PPA Optimization Test Driven Development Scripting +4 more Show less

CPU Power Modeling Microarchitecture Python TCL Perl Benchmark Analysis Workload Characterization +2 more Show less

CPU Architecture Microarchitecture SoC RTL ISA Power Management RAS Debug and Trace Interconnect Protocols Logic Design Firmware Hardware Engineering Low-power Microarchitecture +8 more Show less

RTL Power Modeling PowerArtist PTPX Verilog VHDL Python Perl Clock Gating Logic Design Power Estimation +5 more Show less

RTL Verilog SystemVerilog VHDL LLM Agentic AI CPU Design Microarchitecture Synthesis Simulation Waveform Debug Logic Design +7 more Show less

RTL Verilog VHDL Microarchitecture Logic Design Python Perl Waveform Debugging Simulators Power Management Functional Verification Hardware Engineering Firmware +8 more Show less

SoC Architecture Microarchitecture Power Management Thermal Management RTL Firmware Boot Architecture Logic Design Analog Mixed Signal Hardware Engineering Software Engineering +6 more Show less

RISCV RTL Design Verilog VHDL Microarchitecture Logic Design Power Management Python Perl Waveform Debugging Simulators Hardware Engineering System Architecture +8 more Show less

SoC Microarchitecture RTL NoC RAS DFx Firmware Logic Design Performance Monitoring Telemetry Timer Synchronization Memory Dump Scan-dump +8 more Show less

RTL Verilog VHDL Python Perl Microarchitecture Logic Design Functional Verification Waveform Debugging Instruction Fetch Branch Prediction +6 more Show less

RTL Verilog SystemVerilog Python TCL Perl Bash GIT CI/CD CAD Tools CPU Microarchitecture Hardware Design Automation Scripting +9 more Show less

C Python Java Firmware Ubuntu Server RHEL SUSE Windows Server x86 ARM64 RISC-V BIOS UEFI BMC Firmware Test Automation Validation +11 more Show less