CPU STA CAD Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TX
Salary
$198,700–$298,100 / yr
Posted
11 days ago
Freshness
Confirmed live yesterday
Closes
Feb 27, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k
This role $248k
$138k most similar roles pay here $315k

This role pays more than 88% of similar roles. Most pay $176,162–$226,587 — the shaded band above. At the midpoint, this role pays about $248k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · CPU STA CAD Engineer

As a CPU STA CAD Engineer within the CPU Engineering team, you will build and support advanced analysis tools and flows to ensure custom CPUs achieve industry-leading power, performance, and area. Your daily responsibilities include architecting methodology improvements, maintaining and debugging STA and timing closure flows, and providing guidance to global physical design teams. You will collaborate with EDA vendors to define roadmaps and resolve tool issues while optimizing timing ECO closure. The role requires expertise in Static Timing Analysis on cutting-edge nodes, along with proficiency in Python and Tcl for automation. Key technical skills include Synthesis, PnR, and experience with concepts like LVF/CCS/SSI/NBTI. Additionally, you may apply AI techniques to EDA workflows, including log analysis and automated script generation, to solve complex timing and hardware engineering challenges within the CPU domain.

What you'll do

  • Architect and recommend methodology improvements to optimize silicon power, performance, and area.
  • Maintain, support, and debug Static Timing Analysis (STA) and timing closure (ECO) flows.
  • Resolve project-specific technical issues related to timing and physical design.
  • Provide methodology guidance and tool support to global CPU physical design teams.
  • Collaborate with EDA vendors to define roadmaps and resolve software tool issues.
  • Develop automated scripts and tools using Python and Tcl to improve workflow efficiency.
  • Implement AI techniques for log analysis, root-cause investigation, and automated script generation.

What we're looking for

  • Bachelor's degree plus 6 years of experience, Master's plus 5 years, or PhD plus 4 years in a relevant engineering field.
  • Experience with Static Timing Analysis (STA) on cutting-edge technology nodes.
  • Proficiency in Python and Tcl programming with an automation mindset.
  • Experience generating, optimizing, and automating timing ECO closure.
  • Detailed understanding of STA concepts such as LVF, CCS, SSI, and NBTI.
  • Synthesis/PnR experience with a focus on PPA optimization.
  • Web, database, dashboard, or visualization experience (preferred).
  • Experience applying AI techniques to EDA workflows (preferred).

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