CPU STA CAD Engineer

Qualcomm

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Quick summary

Work type: On-site
Location: Santa Clara, CAAustin, TXSan Diego, CA
Salary: $209,300–$313,900 / yr
Posted: 25 days ago
Freshness: Confirmed live today
Closes: Mar 31, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $262k

$134k $333k

below market most similar roles pay here above market

This role pays more than 95% of similar roles. Most pay $177,250–$233,137 — the blue band above. At the midpoint, this role pays about $262k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · CPU STA CAD Engineer

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The CPU STA CAD Engineer joins the CPU Engineering team to build and support world-class analysis tools and flows for custom CPUs. The role focuses on ensuring industry-leading power, performance, and area by architecting methodology improvements, maintaining STA and timing closure ECO flows, and resolving project-specific issues. Key responsibilities include providing methodology guidance to worldwide physical design teams and collaborating with EDA vendors to define roadmaps. Candidates must possess industry experience in Static Timing Analysis on cutting-edge technology nodes, utilizing Python and Tcl for automation. Required skills include coding for reusability, understanding concepts like LVF, CCS, and NBTI, and experience with Synthesis and PnR for PPA optimization. The position involves solving complex timing closure problems and applying AI techniques to EDA workflows for log analysis and automated script generation.

Skills

Static Timing Analysis (STA) Python Tcl CI/CD ECO Synthesis PnR Test Driven Development AI

What you'll do

Architect and recommend methodology improvements to optimize silicon power, performance, and area.
Maintain, support, and debug Static Timing Analysis (STA) and timing closure (ECO) flows.
Provide methodology guidance and tool support to worldwide CPU physical design teams.
Partner with EDA vendors to define product roadmaps and resolve technical tool issues.
Develop high-quality, reusable code using Python and Tcl with a focus on automation.
Optimize and automate timing ECO closure processes for cutting-edge technology nodes.
Apply AI techniques to EDA workflows for log analysis, root-cause investigation, and script generation.

What we're looking for

Bachelor's degree and 6+ years of relevant engineering experience, Master's degree and 5+ years, or PhD and 4+ years of relevant experience.
Industry experience in Static Timing Analysis (STA) on cutting-edge technology nodes (preferred).
Programming and scripting skills in Python and Tcl with an automation mindset (preferred).
Experience in coding with a focus on quality, reusability, static checking, Test Driven Development, and CI/CD (preferred).
Experience in generating, optimizing, and automating timing ECO closure (preferred).
Detailed understanding of STA concepts such as LVF, CCS, SSI, and NBTI (preferred).
Synthesis and PnR experience with a focus on PPA optimization (preferred).
Experience applying AI techniques to EDA workflows (preferred).