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Active Keyword: ASIC Verification Engineer Remove filter Location: Austin Remove filter Clear all

11 of up to 20 (filtered)

Senior ASIC Verification Engineer

Nvidia

Austin, TX +1 2 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday Posted this week High trust Competitive pay
SystemVerilog UVM VCS GDB RISCV C Assertion-based Verification Functional Coverage Random Stimulus Firmware ASIC Verification Memory Subsystem High Speed IO Object Oriented Programming
5+ yrs exp Hybrid
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Senior ASIC Verification Engineer

Nvidia

Austin, TX 9 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
SystemVerilog UVM RTL Python Perl VCS dc_shell GDB Debussy ASIC Design Pre-silicon Verification Object-Oriented Programming Scripting Design Automation Functional Coverage
5+ yrs exp Hybrid
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Senior ASIC Verification Engineer

Nvidia

Santa Clara, CA +1 9 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
System Verilog UVM C++ Python Perl Formal Verification Constraint Random Verification Coverage Metrics Logic Design ASIC Verification DFT IST Object-Oriented Programming Automation
5+ yrs exp Hybrid
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ASIC Verification Engineer

Nvidia

Austin, TX 9 days ago $116,000–$189,750
Actively hiring Confirmed live yesterday High trust Below market
SystemVerilog UVM RTL Python Perl VCS dc_shell GDB Debussy ASIC Design Pre-silicon Verification Object-Oriented Programming Design Automation Scripting Coverage-based Verification
2+ yrs exp Hybrid
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Senior ASIC Verification Engineer

Nvidia

Austin, TX 9 days ago $136,000–$218,500
Actively hiring Confirmed live 2 days ago High trust Competitive pay
System Verilog UVM RTL Verilog Python VCS Verdi Computer Architecture Functional Coverage Scripting ASIC Verification Simulation Tools
3+ yrs exp
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Senior ASIC Verification Engineer, HSIO

Nvidia

Westford, MA +1 24 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday Trusted Competitive pay
SystemVerilog UVM Ethernet NVLink CXL Python Perl Assertion-based Verification Functional Coverage ASIC Design High Speed I/O Verification Infrastructure Scripting post silicon verification
5+ yrs exp
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Senior ASIC Design Verification Infrastructure and Tools Engineer

Nvidia

Remote (Santa Clara, CA) +3 29 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics
5+ yrs exp Remote
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Senior ASIC Design Verification Engineer

SpaceX

Austin, TX 59 days ago
Actively hiring Confirmed live 2 days ago Low trust
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design
5+ yrs exp
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ASIC Design Verification Engineer

Amazon Inc

Austin, TX +3 78 days ago $136,000–$184,000
Actively hiring Confirmed live 2 days ago High trust Below market
UVM SystemVerilog Verilog SystemC Matlab C DPI-C Formal Verification RTL ASIC Digital Verification Scripting CMOS
5+ yrs exp
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ASIC Design Verification Engineer

Amd

Austin, TX 86 days ago $178,400–$267,600
Actively hiring Confirmed live 2 days ago High trust Above market
System Verilog UVM SystemC Verilog C++ Formal Verification ASIC Design RTL Linux Windows OOP Simulation Functional Coverage Digital Design Computer Architecture
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ASIC Verification Engineer

Nvidia

Austin, TX +1 94 days ago $100,000–$166,750
Actively hiring Confirmed live 2 days ago Low trust Below market
SystemVerilog UVM VCS RISCV C GDB Assertion-based Verification Functional Coverage Random Stimulus Firmware ASIC Verification High Speed IO micro-architecture Object Oriented Programming
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