Senior ASIC Verification Engineer, HSIO

Nvidia

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Westford, MAAustin, TX
Salary: $136,000–$218,500 / yr
Posted: 24 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $191k

This role $177k

$126k most similar roles pay here $230k

This role pays less than 54% of similar roles. Most pay $166,538–$216,062 — the shaded band above. At the midpoint, this role pays about $177k versus about $191k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer, HSIO

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Senior ASIC Verification Engineer - HSIO will join the HSIO Verification team to verify the design and implementation of next-generation High Speed I/O controllers for SOCs and GPUs. The role involves verifying ASIC designs, architectures, golden models, and micro-architecture for components like Ethernet and NVLink at IP and sub-system levels. Responsibilities include building reusable bus functional models, monitors, checkers, and scoreboards using coverage-driven verification methodologies. You will define verification scopes, develop test plans, and build infrastructure to ensure design correctness while collaborating with architects and designers. Required skills include expertise in SystemVerilog, UVM, and assertion-based verification, along with experience in interconnect protocols like Ethernet, USB, or SATA. Preferred technical skills include proficiency in Perl, Python, or other scripting languages, as well as familiarity with CXL and AI-enabled root-cause analysis tools for high-performance computing.

Skills

SystemVerilog UVM Ethernet NVLink CXL Python Perl Assertion-based Verification Functional Coverage ASIC Design High Speed I/O Verification Infrastructure Scripting post silicon verification

What you'll do

Verify ASIC design, architecture, and micro-architecture of High Speed I/O controllers like Ethernet and NVLink.
Implement advanced verification methodologies using UVM at the IP and sub-system levels.
Build reusable bus functional models, monitors, checkers, and scoreboards following coverage-driven methodologies.
Define verification scope and develop comprehensive test plans based on design specifications.
Develop the verification infrastructure required to ensure the correctness of the design.
Execute verification using random stimulus, functional coverage, and assertion-based methodologies.
Perform debugging and root-cause analysis for complex hardware issues.

What we're looking for

Bachelor's or Master's degree (or equivalent experience).
5+ years of relevant experience in design verification.
Expertise in SystemVerilog and UVM at the Unit/Sub-system/SOC level.
Expertise in comprehensive verification of IP or interconnect protocols such as Ethernet, USB, or SATA.
Experience using random stimulus, functional coverage, and assertion-based verification methodologies (UVM).
Excellent debugging, analytical, and problem-solving skills.
Great communication and collaboration skills to interact across functional teams.
Understanding of HSIO-based system architecture, scripting languages like Perl or Python, and AI-enabled tools (preferred).

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