Senior ASIC Verification Engineer

Nvidia

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Westford, MAAustin, TX
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
70 days ago
Freshness
Confirmed live today

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $194k
This role $177k
$125k $236k
below market most similar roles pay here above market

This role pays less than 55% of similar roles. Most pay $171,125–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $194k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Verification Engineer

As a Senior ASIC Verification Engineer - HSIO, you will join the HSIO Verification team to verify the design and implementation of next-generation High Speed I/O controllers for SOCs and GPUs. You will be responsible for verifying ASIC design, architecture, golden models, and micro-architecture for controllers like Ethernet and NVLink at the IP and sub-system levels. Your daily tasks include building reusable bus functional models, monitors, checkers, and scoreboards using UVM. You will define verification scopes, develop test plans, and build verification infrastructure while collaborating with architects and designers. Required skills include SystemVerilog, UVM, and experience with interconnect protocols like Ethernet, USB, or SATA. You will use random stimulus, functional coverage, and assertion-based verification methodologies to ensure the correctness of high-speed interconnect architectures.

What you'll do

  • Verify ASIC design, architecture, and micro-architecture of High Speed I/O controllers using UVM.
  • Build reusable bus functional models, monitors, checkers, and scoreboards using coverage-driven verification.
  • Define verification scope and develop comprehensive test plans based on design specifications.
  • Develop the verification infrastructure required to ensure the correctness of the design.
  • Execute verification of IP and interconnect protocols such as Ethernet, NVLink, and CXL.
  • Utilize random stimulus, functional coverage, and assertion-based verification methodologies.
  • Perform debugging and root-cause analysis to resolve design and implementation issues.

What we're looking for

  • Bachelor's or Master's Degree or equivalent experience.
  • 5+ years of relevant experience.
  • Expertise in SystemVerilog and UVM.
  • Experience at Unit, Sub-system, or SOC levels.
  • Expertise in comprehensive verification of IP or interconnect protocols like Ethernet, USB, or SATA.
  • Experience in verification using random stimulus, functional coverage, and assertion-based verification methodologies.
  • Excellent debugging, analytical, and problem-solving skills.
  • Good understanding of the system level architecture of HSIO-based designs like Ethernet or CXL (preferred).
  • Experience with Perl, Python, or similar scripting and/or SW programming languages (preferred).
  • Experience with AI-enabled code assist or root-cause analysis tools (preferred).

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