Apple Inc

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About Apple Inc

Published by FindRole · most recent listing October 30, 2026 · Methodology

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3542 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2744 roles with salary data.

Most-posted roles

How Apple Inc posts

Employer behavior measured from this employer’s own listings, including ones that have since closed.

77.5%

of open roles publish a salary range

Layoffs · WARN filings

Trending down

1,074 workers affected across 15 filings since 2023.

— 792 — 282

2023 2024 2025 2026

Source: U.S. Worker Adjustment and Retraining Notification (WARN) Act filings, via WARN Feed (CC BY 4.0).

Open roles

3,542 total

Analog IC Design Engineer

Sunnyvale, CA 45 days ago $129,300–$225,300

Actively hiring Confirmed live yesterday Low trust Competitive pay

Analog IC Design ADC DAC Verilog Matlab C Spectrum Analyzers Oscilloscopes Signal Generators ESD Compliance Design for Testability Op-Amps LDOs Switched-Cap Circuits Feedback and Compensation Techniques

Analog IC Design Engineer

Cupertino, CA 45 days ago $129,300–$225,300

Actively hiring Confirmed live 2 days ago Low trust Competitive pay

Analog IC Design ADC DAC Verilog Matlab C Spectrum Analyzers Oscilloscopes Signal Generators ESD Compliance Design for Testability Op-amps LDOs Switched-cap Circuits Feedback and Compensation Techniques

Analog/Mixed-Signal Circuit Design Engineer

Waltham, MA 45 days ago $116,400–$203,000

Actively hiring Confirmed live yesterday Trusted Below market

SERDES ADCs DACs FinFET VerilogA AMS CMOS Spectrum Analyzers Oscilloscopes Signal Generators Mask Design Bench Evaluation Characterization DLLs LDO Regulators Switched-Cap Circuits

Analog IC Design Engineer

Sunnyvale, CA 45 days ago $129,300–$225,300

Actively hiring Confirmed live yesterday Low trust Competitive pay

Analog IC Design ADC DAC Verilog Matlab C ESD Compliance Spectrum Analyzers Oscilloscopes Signal Generators Design for Testability Low Noise Design Op-Amps LDOs Switched-Cap Circuits

Analog IC Design Engineer

Cupertino, CA 45 days ago $129,300–$225,300

Actively hiring Confirmed live 2 days ago Low trust Competitive pay

Analog IC Design ADC DAC Verilog Matlab C Behavioral Modeling ESD Compliance Spectrum Analyzer Oscilloscope Signal Generator Design for Testability Low Noise Design Op-Amps LDOs Switched-Cap Circuits

Mixed-Signal IC Design Engineer

Cupertino, CA 45 days ago $129,300–$225,300

Actively hiring Confirmed live 2 days ago Trusted Competitive pay

Mixed-Signal IC Design SoC Architecture ADC DAC Verilog Python MATLAB C AI ML CMOS Signal Processing Silicon Validation Production Test Device Physics

Mixed-Signal Behavioral Modeling Engineer

Austin, TX 45 days ago

Actively hiring Confirmed live 2 days ago Low trust

SystemVerilog Verilog SPICE Python Perl Digital Logic SERDES Digital Signal Processing Numerical Analysis Formal Equivalence Circuit Simulation

Mixed-Signal Behavioral Modeling Engineer

San Diego, CA 45 days ago $122,700–$214,300

Actively hiring Confirmed live 2 days ago Low trust Below market

SystemVerilog Verilog Python Perl SPICE Digital Logic Formal Equivalence Digital Signal Processing Numerical Analysis ADCs DACs PLLs DLLs SERDES Circuit Simulation

Mixed-Signal Behavioral Modeling Engineer

Cupertino, CA 45 days ago $129,300–$225,300

Actively hiring Confirmed live yesterday Low trust Below market

SystemVerilog Verilog Python Perl SPICE Digital Logic SERDES Digital Signal Processing Numerical Analysis Formal Equivalence Circuit Simulation

PLL Design Engineer

Austin, TX 45 days ago

Actively hiring Confirmed live 2 days ago Trusted

PLL FLL Frequency Synthesis VCO DCO Fractional-N System Verilog RTL Jitter Analysis Op-Amps LDOs Scripting SOC SerDes

ESD Engineer

San Diego, CA 45 days ago $122,700–$214,300

Actively hiring Confirmed live yesterday Low trust Competitive pay

ESD Latch-Up Transistor Device Characteristics HBM CDM MM IEC-61000-4-2 Virtuoso Calibre Allegro EDA Tools Circuit Design Test Structures Characterization

ESD Engineer

Austin, TX 45 days ago

Actively hiring Confirmed live 2 days ago High trust

ESD Latch-Up HBM CDM MM IEC-61000-4-2 Virtuoso Calibre Allegro EDA Tools Circuit Design Layout Test Structures Characterization

ESD Engineer

Austin, TX 45 days ago

Actively hiring Confirmed live yesterday High trust

ESD Latch-Up HBM CDM MM IEC-61000-4-2 Virtuoso Calibre Allegro EDA Tools Circuit Design Layout Test Structures Characterization

DDR Design Engineer

Waltham, MA 45 days ago $116,400–$203,000

Actively hiring Confirmed live yesterday Low trust Below market

Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Constraints Unified Power Format Equivalence Checking DFT Scan Concept Clock Domain Crossing

Software & Tools Engineering Project Manager

Austin, TX 45 days ago

Actively hiring Confirmed live 2 days ago High trust

Agile Jira Confluence Wrike PMO Project Management Change Management Software Development Metrics Program Governance PMP PMI-ACP CSM

5+ yrs exp

CPU Design Verification Engineer

Beaverton, OR 45 days ago

Actively hiring Confirmed live 2 days ago Low trust

SystemVerilog C C++ Assembly CPU Architecture Digital Logic Design Microarchitecture Post-silicon Bringup RTL Design Transactors

3+ yrs exp

CPU Debug and Power Management Verification Engineer

Beaverton, OR 45 days ago

Actively hiring Confirmed live 2 days ago Low trust

SystemVerilog UVM SVA Python Perl C++ Assembly AXI UPF FPGA Emulation Formal Verification Post-Silicon Debug Simulation Power Management Clock Control Hardware Trace

10+ yrs exp

CPU Debug and Power Management Verification Engineer

Beaverton, OR 45 days ago

Actively hiring Confirmed live yesterday Low trust

SystemVerilog UVM SVA Python C++ Assembly Perl AXI UPF FPGA Emulation Formal Verification Post-Silicon Debug Power Management Clock Control RTL Simulation

3+ yrs exp

CPU Design Verification Engineer

Beaverton, OR 45 days ago

Actively hiring Confirmed live yesterday Low trust

SystemVerilog C C++ Assembly CPU Architecture Digital Logic Design Microarchitecture Post-silicon Bringup RTL Design

10+ yrs exp

CPU Technology Feasibility Implementation Engineer

Austin, TX 45 days ago

Actively hiring Confirmed live yesterday Low trust

RTL-to-GDS Flow Synthesis place-and-route PnR PPA Optimization CPU Microarchitecture Clock Flow Physical Design Memory Design Process Technology Evaluation

10+ yrs exp