PLL Design Engineer

As a PLL Design Engineer within the Analog-Mixed/Signal group, you will develop cutting-edge frequency synthesizers for diverse applications including Compute, SoC, SerDes, and Cellular technologies. You will be responsible for designing and developing high-quality hard IPs to address the escalating complexity of SOC/PHY designs. Your daily work involves circuit design for PLL/FLL and frequency synthesis architectures using both digital and analog approaches. Key technical tasks include DCO/VCO design (RO and LC), Fractional-N, SSC, and spur and jitter cancellation techniques. You will also work with band gaps, bias circuits, op-amps, LDOs, and feedback compensation. To support these goals, you will develop System Verilog models, perform behavioral simulations to analyze loop dynamics, and utilize scripting skills alongside industry-standard design tools to solve complex technical problems in the frequency synthesis domain.