This role pays more than
67%
of similar roles. Most pay
$142,575–$193,000
— the shaded band above.
At the midpoint, this role pays about
$177k
versus about
$168k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
598 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 586 roles with salary data.
The Senior Design Engineer joins the Artificial Intelligence System on Chip (AISoC) Silicon team to drive high performance, high bandwidth Network-on-Chip designs for state-of-the-art AI SoCs. This role involves developing Intellectual Property microarchitecture specifications, performing Register Transfer Level design, and managing synthesis, Lint, CDC, and FEV processes while ensuring successful System on Chip integration across various subsystems. The engineer will collaborate with architecture, verification, and physical design teams to ensure designs meet specific requirements. Key technical competencies include Verilog and System Verilog coding, Clock Domain Crossing closure, and navigating PPA trade-offs for complex control logic or networking ASICs. The work focuses on the specialized domain of designing fabrics and networks specifically optimized for AI usage, including experience with CPU or graphics core design and complex algorithmic designs for artificial intelligence applications.
Develop microarchitecture specifications for high-performance Network-on-Chip designs in AI SoCs.
Create Register Transfer Level (RTL) designs using Verilog or SystemVerilog.
Perform synthesis, Lint, Clock Domain Crossing (CDC), and FEV checks on various subsystems.
Manage System on Chip (SoC) integration across different hardware components.
Execute PPA trade-offs involving power, performance, area, and timing constraints.
Conduct post-silicon debug to ensure design integrity and functionality.
Coordinate with architecture, verification, and physical design teams to meet technical specifications.
What we're looking for
A Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of technical engineering experience.
A Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of technical engineering experience.
A Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of technical engineering experience.
Equivalent experience to the specified degree and experience requirements.
Ability to pass a Microsoft Cloud background check every two years.
Must provide proof of citizenship, residency, or other protected status to access export-controlled information.
8+ years expertise in Digital Design including microarchitecture specification, RTL coding in Verilog/System Verilog, and CDC/Lint closure (preferred).
6+ years experience delivering successful IP or ASIC/SoC designs; 4+ years in Synthesis, PPA trade-offs, Post-Silicon Debug, Fabric/NoC design, or complex control logic (preferred).