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Active Keyword: CDC Remove filter Clear all

8 of up to 20 (filtered)

Low-Power & CDC Verification Engineer

Amd

Santa Clara, CA 12 days ago $118,400–$177,600
Actively hiring Confirmed live today High trust Below market
Formal Verification RTL Power/Clock Domain Crossing UPF Python Perl Simulation Emulation Digital Design Processor Architecture Tape out Verification
1+ yrs exp
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ASIC DFT Technical Leader, CDC

Cisco

San Jose, CA +2 14 days ago $186,900–$267,700
Actively hiring Confirmed live today High trust Above market
ASIC RTL CDC RDC SDC VCS SVA SystemVerilog Synthesis Gate Netlists
8+ yrs exp Hybrid
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CPU CDC/RDC/STA Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live yesterday Trusted
CDC RDC STA SystemVerilog Assertions Verilog TCL Perl Synopsys Real Intent Spyglass VC-Static PrimeTime Meridian RTL Design Design Verification
10+ yrs exp
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CPU CDC/STA Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
Static Timing Analysis (STA) Clock Domain Crossing (CDC) Reset Domain Crossing (RDC) SystemVerilog Assertions (SVA) TCL Perl Verilog Spyglass VC-Static PrimeTime Meridian Design Verification Lint RTL
3+ yrs exp
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CPU CDC/STA Engineer

Apple Inc

Santa Clara, CA 40 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
Static Timing Analysis (STA) Clock Domain Crossing (CDC) Reset Domain Crossing (RDC) SystemVerilog Assertions (SVA) TCL Perl Verilog Spyglass VC-Static PrimeTime Meridian Design Verification Lint RTL
3+ yrs exp
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CPU CDC/RDC/STA Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
CDC RDC STA SystemVerilog Assertions Verilog TCL Perl Synopsys Real Intent Spyglass VC-Static PrimeTime Meridian RTL Design Design Verification Lint
10+ yrs exp
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CPU CDC/RDC/STA Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live yesterday Trusted
CDC RDC STA SystemVerilog Assertions Verilog TCL Perl Synopsys Real Intent Spyglass VC-Static PrimeTime Meridian RTL Design Design Verification
10+ yrs exp
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CPU CDC/STA Engineer

Apple Inc

Santa Clara, CA 40 days ago $129,300–$194,700
Actively hiring Confirmed live today Trusted Below market
Static Timing Analysis (STA) Clock Domain Crossing (CDC) Reset Domain Crossing (RDC) SystemVerilog Assertions (SVA) Verilog TCL Perl Spyglass VC-Static PrimeTime Meridian Design Verification (DV) Lint RTL
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