Principal Subsystem Design Engineer

Microsoft

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$142,800–$274,800 / yr
Posted
3 days ago
Freshness
Confirmed live yesterday
Closes
Mar 7, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $185k
This role $209k
$126k most similar roles pay here $291k

This role pays more than 73% of similar roles. Most pay $155,998–$214,000 — the shaded band above. At the midpoint, this role pays about $209k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 598 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 586 roles with salary data.

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At a glance

TL;DR · Principal Subsystem Design Engineer

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The Principal Subsystem Design Engineer joins the Artificial Intelligence System on Chip team within the Silicon, Cloud Hardware, and Infrastructure Engineering group. This role provides technical leadership for Memory Subsystem development, driving solutions from architecture and microarchitecture through silicon bring-up. The engineer will design, integrate, and verify high-performance SoC subsystems while collaborating with cross-functional teams to resolve system-level issues. Key responsibilities include optimizing architectures involving PCIe, HBM, interconnect fabrics, AMBA AXI/CHI protocols, DMA engines, and NoCs. The role requires expertise in Verilog, SystemVerilog, and scripting languages like Python or Perl to perform RTL development, synthesis, and timing constraints. This position focuses on the technical challenge of developing high-performance, scalable hardware for cloud infrastructure, specifically addressing memory technologies, bandwidth, latency, power efficiency, and performance optimization within complex Artificial Intelligence and Machine Learning SoC environments.

Skills

Verilog SystemVerilog RTL Design SoC PCIe HBM AMBA AXI DMA Synthesis Timing Constraints CDC Lint RDC DFT Python Perl Agile Post-Silicon Debug

What you'll do

  • Provide technical leadership for Memory Subsystem development from architecture through silicon bring-up.
  • Lead the design, integration, and verification of high-performance SoC subsystems focusing on memory technologies.
  • Develop and optimize architectures involving PCIe, HBM, interconnect fabrics, and DMA engines.
  • Drive microarchitecture specification and RTL development using Verilog or SystemVerilog.
  • Manage design quality closure including synthesis, timing constraints, floor-planning, and CDC/lint checks.
  • Debug complex design and system-level issues across simulation, emulation, and silicon environments.
  • Drive vertical and horizontal IP reuse to ensure scalable and efficient subsystem architectures.

What we're looking for

  • A Doctorate in Electrical Engineering, Computer Engineering, or Computer Science with 3+ years of technical engineering experience.
  • A Master's degree in Electrical Engineering, Computer Engineering, or Computer Science with 6+ years of technical engineering experience.
  • A Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science with 8+ years of technical engineering experience.
  • Equivalent professional experience to the specified educational and experience requirements.
  • Ability to pass a Microsoft Cloud background check and meet export control regulations for access to restricted information.
  • Proof of citizenship, U.S. residency, or other protected status is required for export control eligibility.
  • 9+ years of experience in RTL design with a track record of delivering high-performance IP, SS, or SoC designs like PCIe, DDR, or HBM.
  • Expertise in microarchitecture specification, RTL coding, synthesis, timing constraints, and post-silicon debug.

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