This role pays more than
68%
of similar roles. Most pay
$173,371–$225,075
— the shaded band above.
At the midpoint, this role pays about
$209k
versus about
$199k
for comparable roles.
Based on 240 similar postings.
Employer
About Microsoft
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has
598 open roles
on FindRole.
Listed pay typically runs
$119,800–$234,700
across 586 roles with salary data.
The Principal Design Engineer joins the Artificial Intelligence System on Chip (AISoC) Silicon team within the Cloud Hardware, and Infrastructure Engineering group. In this role, you will drive high performance and high bandwidth designs by focusing on Intellectual Property microarchitecture specification, Register Transfer Level design, synthesis, and System on Chip integration across various subsystems. You will collaborate with architecture, verification, and physical design teams to ensure implementations meet specific requirements. The position requires expertise in Verilog, System Verilog, and Clock Domain Crossing closure, alongside experience in Synthesis, Timing constraints, Power, Performance, Area trade-offs, and Post-Silicon Debug. You will work on complex algorithmic designs for AI usages, Fabric or Network On Chip designs, and potentially CPU or graphics core designs to solve technical challenges within the specialized domain of AI silicon infrastructure.
Develop microarchitecture specifications for high-performance, high-bandwidth Intellectual Property (IP).
Create Register Transfer Level (RTL) designs using Verilog or SystemVerilog.
Perform synthesis and manage Power, Performance, and Area (PPA) trade-offs.
Execute System on Chip (SoC) integration across various subsystems.
Ensure design compliance with specifications through coordination with architecture, verification, and physical design teams.
Resolve Clock Domain Crossing (CDC) and Lint issues during the design process.
Implement complex algorithmic designs specifically for Artificial Intelligence applications.
Develop scripts to support silicon engineering workflows and automation.
What we're looking for
A Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of technical engineering experience.
A Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of technical engineering experience.
A Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years of technical engineering experience.
Equivalent professional experience to the degrees listed above.
Ability to pass Microsoft Cloud background checks and meet government security screening requirements.
Ability to provide proof of citizenship or protected status for access to export-controlled information.
12+ years expertise in Digital Design including microarchitecture, Verilog/System Verilog coding, and CDC/Lint closure (preferred).
Experience in ASIC/SOC design, Synthesis, PPA trade-offs, Post-Silicon Debug, Fabric/Network On Chip, or AI algorithmic designs (preferred).
Computer Vision
Deep Learning
Python
C++
PyTorch
TensorFlow
Keras
Caffe
Linux
Android
QNX
Quantization
Pruning
Distillation
CPU
GPU
DSP
NPU
Containerization