Senior Design Engineer

Arm Holdings

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Hybrid

Quick summary

Work type
Hybrid
Location
San Diego, CA
Salary
$161,500–$218,500 / yr
Posted
40 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $174k
This role $190k
$126k $228k
below market most similar roles pay here above market

This role pays more than 70% of similar roles. Most pay $149,443–$198,944 — the blue band above. At the midpoint, this role pays about $190k versus about $174k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 113 open roles on FindRole.

Listed pay typically runs $208,450–$282,050 across 112 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Senior Design Engineer

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The Senior Design Engineer joins an innovative team to integrate PCIe, DDR, and other IPs into complex SoCs and compute platforms. This role involves writing micro-architecture specifications, developing RTL, fixing bugs, and running design checks while collaborating with verification, performance analysis, and backend implementation teams. Key responsibilities include developing build specifications, performing floor planning, writing constraints, and ensuring timing closure. The ideal candidate possesses a degree in Computer Science or Electrical Engineering and over seven years of experience in digital hardware design. Required technical skills include Verilog HDL, Perl, Python, and experience with Static design checks like CDC and Linting. The work focuses on solving complex compute subsystem challenges, specifically involving DDR/LPDDR, HBM, UCIe, and Ethernet integration within advanced SoC architectures.

Skills

SoC RTL Verilog HDL SystemVerilog ARM PCIe DDR LPDDR HBM UCIe Ethernet Python Perl UVM OVM CDC Linting Synthesis DFT

What you'll do

  • Integrate PCIe, DDR, and other IP subsystems into SoCs.
  • Write micro-architecture specifications and develop RTL for SoC projects.
  • Fix bugs and run various design checks including CDC, RDC, and Linting.
  • Review test plans and debug build issues with the verification team.
  • Evaluate and improve system performance in partnership with the performance analysis team.
  • Assist with floor planning, writing constraints, and timing closure for backend implementation.
  • Develop and enhance design methodologies used by the engineering team.

What we're looking for

  • Bachelor's or Master's degree in Computer Science, Electrical/Computer Engineering, or a related field.
  • 7+ years of experience in the design of complex compute subsystems or SoCs.
  • Strong knowledge of digital hardware design and Verilog HDL.
  • Experience developing and integrating subsystems for PCIe, DDR/LPDDR, HBM, UCIe, and Ethernet.
  • Experience creating design specifications and developing RTL for SoC projects and compute platforms.
  • Experience in static design checks, including CDC, RDC, X-Propagation, and Linting.
  • Experience with Perl, Python, or other scripting languages.
  • Experience with ARM-based designs, SystemVerilog, UVM/OVM, synthesis, or power management (preferred).

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