below marketmost similar roles pay hereabove market
This role pays more than
54%
of similar roles. Most pay
$154,607–$216,250
— the blue band above.
At the midpoint, this role pays about
$190k
versus about
$185k
for comparable roles.
Based on 240 similar postings.
Employer
About Arm Holdings
Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.
Arm Holdings currently has
113 open roles
on FindRole.
Listed pay typically runs
$208,450–$282,050
across 112 roles with salary data.
The Senior Security IP Design Engineer joins the Solutions Engineering Security IP Team to develop architectures, specifications, and sophisticated hardware functions for pioneering SoC designs. This role involves developing Security IP and subsystems, including RTL and constraint development, bug fixing, and leading design exploration and optimization. The engineer will partner with verification and implementation peers to drive closure, support debug, and achieve functional, power, and performance sign-off. Key technical requirements include expertise in Verilog RTL design, Applied Cryptography, Secure Boot, Key Management, and Access Controls. Candidates must be proficient in AXI/AHB protocols, synthesis, timing analysis, and power management techniques like UPF. Required skills include experience with SystemVerilog, UVM/OVM, and scripting languages such as Perl, Python, and TCL within ARM-based designs.
Develop architectures, specifications, and design sophisticated security hardware functions.
Create RTL and constraints for security IP and subsystems.
Perform bug fixing and lead design exploration, optimization, and structural checks.
Build test plans and drive verification closure with implementation peers.
Support debug efforts to achieve functional, power, and performance sign-off.
Contribute to the development and enhancement of team processes and methodologies.
Mentor team members and manage project roadmaps, initiatives, and schedules.
What we're looking for
Preferred candidates should have a Bachelor's or Graduate degree in Computer Science or Electrical/Computer Engineering (preferred).
Applicants must have a track record of leadership in the design and productization of Compute, Multimedia, or Security Sub-Systems and SoCs.
Candidates must have an advanced understanding of hardware Verilog RTL design, verification, and EDA methodologies.
Applicants must have proven experience in Security Hardware, Embedded Processor Systems, Applied Cryptography, Secure Boot, Key Management, and Access Controls.
Candidates must have proven experience in SoC architecture including multi-clock domains, AXI/AHB protocols, multi-power domains, and reset architectures.
Applicants must have competency with synthesis, timing analysis, constraints development, and ECO methodologies.
Candidates must be familiar with design checks including CDC, RDC, X-Propagation, and LINT.
Applicants must be familiar with power management techniques, UPF, power estimation, and power optimization.
Candidates must have experience with Perl, Python, TCL, or other scripting languages.
Applicants must have familiarity with ARM-based designs and/or ARM System Architectures.
Candidates must have experience with SystemVerilog and verification methodologies such as UVM/OVM, Portable Stimulus, and Hardware/Firmware co-verification.
UVM
System Verilog
Python
CHI
AMBA
AXI
PCIe
CXL
Generative AI
IP Verification
random-stimulus
Simulation
Test Bench
Protocol Bridges
Power Management
Virtualization
AI Security
AI Red Teaming
AI Guardrails
AI Security Posture Management (AI SPM)
Model Evaluation
OWASP Top 10 for LLM
NIST
ISO
Incident Response
Security Architecture
Cloud Security
CISSP
GIAC
CEH
OSCP