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Next-Gen High-Speed HBM LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture
4+ yrs exp
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Next-Gen High-Speed HBM LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture
4+ yrs exp
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Senior RTL Design Engineer, DDR/LPDDR Memory Controller

Amd

Austin, TX +2 109 days ago $178,400–$267,600
Actively hiring Confirmed live yesterday High trust Above market
RTL Design Verilog SystemVerilog Python Perl Tcl Digital Logic Design Computer Architecture DDR LPDDR EDA Tools Lint CDC Timing Analysis Synthesis Simulation IP Microarchitecture
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