Principal Engineer, SOC Design

Samsung Semiconductor

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Quick summary

Work type
On-site
Location
San Jose, CAFolsom, CA
Salary
$219,000–$351,000 / yr
Posted
54 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $210k
This role $285k
$138k $374k
below market most similar roles pay here above market

This role pays more than 89% of similar roles. Most pay $177,250–$243,247 — the blue band above. At the midpoint, this role pays about $285k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 36 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 36 roles with salary data.

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At a glance

TL;DR · Principal Engineer, SOC Design

Role Posting Log in to save

The Principal Engineer, SOC Design joins the DRAM Development Lab within the Memory Business Unit to develop silicon solutions for cloud and data center environments. This role focuses on creating new computing system architectures to support emerging machine learning applications, data analytics, and edge computing by developing prototype and production controllers. Key responsibilities include participating in architectural definitions, performing top integration, logic design, and RTL implementation, and conducting quality checks such as Assertion, Lint, CDC, and STA. The candidate will review and integrate third-party IPs including ARM cores, DDR controllers, and UCIe PHYs. Required technical expertise includes ASIC design flow from design to tape out, ATE vector generation, silicon bring up, AMBA bus fabric, and PPA trade-offs.

Skills

ASIC Design RTL SoC ARM DDR UCIe AMBA DFT Static Timing Analysis Synthesis Lint CDC Assertion ATE silicon bring up PPA Ethernet

What you'll do

  • Participate in architectural definitions and define micro-architectures for subsystems and chip levels.
  • Perform top integration, logic design, and RTL implementation for silicon solutions.
  • Execute quality checks including Assertion, Lint, CDC, and Static Timing Analysis (STA).
  • Review and integrate third-party IPs such as ARM cores, DDR controllers, and UCIe PHYs.
  • Coordinate with physical designers on timing constraints, synthesis, and DFT insertion.
  • Manage interfacing with third-party service companies for DFT, PI, and PD tasks.
  • Generate ATE vectors and lead testing and silicon bring-up processes.

What we're looking for

  • Bachelors in Electrical or Computer Science with 20+ years of experience, Masters with 18+ years, or PhD with 15+ years preferred.
  • Hands-on experience in the full ASIC design flow from design to tape out.
  • Experience in SoC level synthesis, timing analysis, lint checks, and CDC checks.
  • Experience with commercial IPs including UCIe, CPU, Ethernet, and DDR interfaces.
  • Knowledge and experience in AMBA bus fabric and ARM cores.
  • Experience in ATE vector generation, testing, and silicon bring-up.
  • Experience interfacing with third-party service companies for DFT, PI, and PD.
  • Good understanding of PPA (performance, power, and area) trade-offs.

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