Principal Engineer, SOC Design

Samsung Semiconductor

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CAFolsom, CA
Salary
$219,000–$351,000 / yr
Posted
8 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k
This role $285k
$122k most similar roles pay here $376k

This role pays more than 93% of similar roles. Most pay $174,600–$227,500 — the shaded band above. At the midpoint, this role pays about $285k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 49 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 49 roles with salary data.

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At a glance

TL;DR · Principal Engineer, SOC Design

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As a Principal Engineer, SOC Design within the DRAM Development Lab, you will join the SOC team to develop silicon solutions and create new computing system architectures for machine learning applications, data analytics, and edge computing. You will be responsible for architectural definitions, micro architecture of subsystems or chips, top integration, logic design, and RTL implementation including quality checks like Assertion, Lint, CDC, and STA. Your daily work involves reviewing third-party IPs such as ARM cores, DDR controllers, and UCIe PHYs while collaborating with physical designers on timing constraints, synthesis, and DFT insertion. You will utilize expertise in ASIC design flows, ATE vector generation, silicon bring up, and AMBA bus fabric. The role focuses on enhancing memory and storage capabilities by developing prototype and production controllers to solve critical cloud and data center problems.

What does a Engineer earn in California?

Median $208000 from 94 postings across 22 companies.

See salary data

Skills

ASIC RTL SoC ARM DDR UCIe Ethernet AMBA DFT STA Synthesis Lint CDC PPA silicon bring up ATE Logic Design

What you'll do

  • Define micro-architectures for subsystems and chip-level components.
  • Perform top integration, logic design, and RTL implementation.
  • Conduct quality checks including Assertion, Lint, CDC, and STA.
  • Review and integrate third-party IPs such as ARM cores, DDR controllers, and UCIe PHYs.
  • Collaborate with verification engineers to ensure sound SoC-level designs.
  • Coordinate with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis.
  • Manage the ASIC design flow from initial design through tape-out.
  • Oversee ATE vector generation, testing, and silicon bring-up processes.

What we're looking for

  • Bachelor's degree in Electrical, Computer Science, or related field with 20+ years of experience.
  • Master's degree in Electrical, Computer Science, or related science with 18+ years of industry experience.
  • PhD in Electrical, Computer Science, or related science with 15+ years of industry experience.
  • Hands-on knowledge and experience in the ASIC design flow from design to tape out.
  • Experience in ATE vector generation, testing, and silicon bring up.
  • Experience with commercial IPs including UCIe, CPU, Ethernet, and DDR interfaces.
  • Proficiency in SoC level synthesis, timing analysis, lint checks, and CDC checks.
  • Knowledge of AMBA bus fabric and ARM cores.

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