Principal Engineer, SOC Integration

Samsung Semiconductor

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Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $219,000–$351,000 / yr
Posted: 96 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $189k

This role $285k

$110k $377k

below market most similar roles pay here above market

This role pays more than 95% of similar roles. Most pay $161,272–$216,253 — the blue band above. At the midpoint, this role pays about $285k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 36 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 36 roles with salary data.

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At a glance

TL;DR · Principal Engineer, SOC Integration

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The Principal Engineer, SOC Integration joins the SOC team within the DRAM Development Lab to create new computing system architectures for emerging machine learning applications, data analytics, and edge computing. This role focuses on enhancing memory and storage capabilities by developing prototype and production controllers. Key responsibilities include owning the integration of SoCs with high-speed interfaces, reviewing third-party IPs like ARM cores, DDR controllers, and UCIe PHYs, and integrating these components with system buses, peripherals, and CPU cores. The position requires expertise in ASIC design flows from design to tape out, including SoC level synthesis, timing analysis, lint checks, and CDC checks. Candidates must demonstrate proficiency with AMBA bus fabric, Ethernet interfaces, and PPA trade-offs to ensure sound design at the SoC level.

Skills

ASIC Design SoC Integration ARM DDR UCIe AMBA Static Timing Analysis Synthesis DFT Lint Check CDC Check Ethernet PPA Tape out Machine Learning Data Analytics

What you'll do

Own the integration of SoCs with multiple high-speed interfaces.
Review third-party IPs including ARM cores, DDR controllers, and UCIe PHYs.
Integrate third-party IPs with system buses, peripherals, and CPU cores.
Coordinate with architects and verification engineers to ensure sound SoC-level design.
Work with physical designers on timing constraints, synthesis, and DFT insertion.
Perform static timing analysis, lint checks, and CDC checks.
Develop prototype and production controllers to enhance memory and storage capabilities.

What we're looking for

BS in Computer/Electrical Engineering or Computer Science with 20+ years of experience.
MS in Computer/Electrical Engineering or Computer Science with 18+ years of experience.
Hands-on knowledge and experience in ASIC design flow from design to tape out.
Experience in commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.
Experience in SoC level synthesis, timing analysis, lint check, and CDC checks.
Knowledge and experience in AMBA bus fabric, ARM CPU cores, and ARM Co-sight debug features.
Good understanding of PPA (performance, power, and area) trade-offs.
Ability to work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis.

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