SOC Design Verification Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$121,800–$182,600 / yr
Posted
21 days ago
Freshness
Confirmed live today
Closes
Apr 4, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $152k
$109k $243k
below market most similar roles pay here above market

This role pays less than 90% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $152k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · SOC Design Verification Engineer

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The SOC Design Verification Engineer joins the Data Center SoC Verification team to verify next-generation SoCs for AI, high-performance computing, and cloud infrastructure. The engineer develops and executes comprehensive verification plans for SoC, subsystem, and IP-level features, ensuring first-silicon success. Daily responsibilities include designing scalable System Verilog/UVM-based and Processor-based verification environments, creating directed and constrained-random test scenarios, and developing assertions, functional coverage models, and checkers. The role requires debugging RTL and testbench issues while driving coverage closure. Key technologies include System Verilog, UVM, C, Assertion-Based Verification, and Python for automation. The work involves verifying complex features such as multi-core CPU systems, cache coherency, DDR/HBM memory subsystems, PCIe, CXL, Ethernet, and security features within advanced SoC architectures.

Skills

System Verilog UVM C Assertion-Based Verification (SVA) Coverage-Driven Verification Python Formal Verification Portable Stimulus (PSS) PCIe CXL DDR HBM Ethernet Veloce Palladium ZeBu RTL SoC Architecture AI/ML Accelerators

What you'll do

  • Develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features.
  • Design and implement scalable System Verilog/UVM-based and Processor-based verification environments.
  • Create directed and constrained-random test scenarios to validate functionality and architectural use cases.
  • Develop assertions, functional coverage models, and checkers to ensure design integrity.
  • Debug RTL, testbench, and integration issues to resolve defects in collaboration with design teams.
  • Drive coverage closure using functional and code coverage metrics.
  • Verify complex features including multi-core CPUs, cache coherency, memory subsystems, and high-speed interfaces.
  • Support emulation and acceleration-based verification and contribute to methodology automation.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, or integration experience.
  • Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, or integration experience.
  • PhD in Science, Engineering, or related field.
  • Strong knowledge of System Verilog, UVM, C, Assertion-Based Verification (SVA), Coverage-Driven Verification, and System level Use case verification.
  • Experience developing verification environments from architecture/specification through signoff.
  • Strong understanding of computer architecture and digital design fundamentals.
  • Experience debugging complex SoC-level issues.
  • Experience with CPU, cache coherency, memory systems, networking protocols, or AI/ML accelerator verification (preferred).

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