Senior Memory Controller Verification Engineer

Nvidia

Confirmed live today Low trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAWestford, MAAustin, TXHillsboro, ORSeattle, WA
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 96 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k

This role $216k

$131k $279k

below market most similar roles pay here above market

This role pays more than 78% of similar roles. Most pay $170,750–$216,250 — the blue band above. At the midpoint, this role pays about $216k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Memory Controller Verification Engineer

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The Senior Memory Controller Verification Engineer joins the GPU Memory Subsystem IP verification team to ensure functional correctness and performance for complex design units. In this role, you will partner with design and architecture teams to make implementation choices, craft verification test plans, and maintain regressions to close coverage. Daily responsibilities include developing verification infrastructure such as testbenches, BFMs, checkers, monitors, and randoms while driving test plan execution for planned features. You will utilize SystemVerilog and UVM based methodology alongside tools like VCS, Debussy, and GDB. Candidates should possess experience with dynamic memory controllers including DDR, LPDDR, HBM, or GDDR. The work involves verifying RTL, enabling FPGA and software teams, and participating in post-silicon verification and debug for GPU and AI technology.

Skills

System Verilog UVM ASIC Verification C++ C Python Perl Shell VCS Debussy GDB FPGA Post-Silicon Verification RTL Memory Controllers DDR LPDDR HBM GDDR

What you'll do

Develop verification infrastructure including testbenches, BFMs, checkers, monitors, and random generators.
Create and drive the execution of test plans for planned IP features.
Develop and execute performance test plans to meet specific IP requirements.
Ensure full code and functional coverage of all verified RTL.
Coordinate with FPGA and software teams to ensure comprehensive software testing.
Plan for and participate in post-silicon verification and debugging activities.
Sign off on design functional correctness and performance expectations.

What we're looking for

BS / MS or equivalent experience.
6+ years of ASIC verification experience of complex design units.
Background with System Verilog and UVM based methodology for ASIC verification.
Exposure to design and verification tools such as VCS, Debussy, or GDB.
Strong C/C++ programming experience (preferred).
Prior Design or Verification experience of dynamic memory controllers (preferred).
Scripting knowledge in Python, Perl, or shell (preferred).
Strong debugging and problem solving skills (preferred).

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