Senior Memory Controller Verification Engineer

Nvidia

Confirmed live 2 days ago Trusted

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAWestford, MAAustin, TXHillsboro, ORSeattle, WA
Salary: $168,000–$264,500 / yr
Posted: 50 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k

This role $216k

$137k most similar roles pay here $278k

This role pays more than 79% of similar roles. Most pay $175,000–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Memory Controller Verification Engineer

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The Senior Memory Controller Verification Engineer joins the GPU Memory Subsystem IP verification team to ensure functional correctness and performance for memory controllers. In this role, you will partner with design and architecture teams to make implementation choices, develop verification infrastructure including testbenches, BFMs, checkers, monitors, and randoms, and execute comprehensive test plans. You will manage code and functional coverage of RTL while collaborating with FPGA and software teams for testing and post-silicon debug. The role requires expertise in SystemVerilog and UVM methodology, along with experience using VCS or equivalent simulation tools and debug tools like Debussy or GDB. Preferred skills include C/C++ programming, scripting in Python, Perl, or shell, and specific experience with dynamic memory controllers such as DDR, LPDDR, HBM, or GDDR to solve complex hardware verification challenges.

Skills

System Verilog UVM VCS C++ C Python Perl Shell FPGA RTL Post-silicon Verification DDR LPDDR HBM GDDR GDB Debussy

What you'll do

Develop verification infrastructure including testbenches, BFMs, checkers, monitors, and random generators.
Create, review, and drive the execution of test plans for planned features.
Define and execute performance test plans to meet specific IP requirements.
Ensure full code and functional coverage of all RTL being verified.
Coordinate with FPGA and software teams to ensure comprehensive software testing.
Participate in post-silicon verification and debugging activities.
Partner with design and architecture teams to influence implementation choices.

What we're looking for

BS/MS degree or equivalent experience in engineering.
6+ years of ASIC verification experience for complex design units.
Proficiency with SystemVerilog and UVM based methodology for ASIC verification.
Experience with design and verification tools such as VCS, Debussy, or GDB.
Strong C/C++ programming experience.
Knowledge of scripting languages including Python, Perl, or shell.
Prior experience in the design or verification of dynamic memory controllers like DDR, LPDDR, HBM, or GDDR.

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