Browse tech roles

TypeScript React CI/CD Unit Testing Integration Testing RxJS REST APIs WebSockets Git Visual Regression Testing State Management Mocking Frameworks SaaS UI Architecture +9 more Show less

Generative AI GenAI Machine Learning AI ML Data Processing Model Building Data Science Research +4 more Show less

Configuration Management Windchill Product Data Management (PDM) MIL-HDBK-61 DoD Standards MS Office Suite Artificial Intelligence Blockchain Firmware Network Switches Build Documentation +6 more Show less

Software Defined Vehicles (SDV) Embedded Software Cloud-native Edge Architecture AI Data DevSecOps ALM–PLM OTA E/E Architecture Systems Integration Validation & Verification Software Lifecycle Management Digital Engineering Managed Services +10 more Show less

C C++ Python Verilog SystemVerilog Perl Matlab Vulkan UVM RTL ASIC SoC DSP LTE 5G Wi-Fi Linux Windows Machine Learning +14 more Show less

DFT SoC Python Perl TCL Gate Level Simulation Coverage Analysis Assertions Test Benches Random Verification Logic Design Automation Scripts +7 more Show less

DFT SoC Python Perl TCL Gate Level Simulation Coverage Analysis Assertions Test Benches Random Verification Logic Design Automation Scripts +7 more Show less

DFT SoC Gate Level Simulation Python Perl TCL Random Verification Coverage Analysis Assertions Logic Design Test Benches Automation Scripts +7 more Show less

DFT Design Verification Python Perl TCL Gate Level Simulation Coverage Analysis Assertions Object-Oriented Programming Pre-silicon Logic Design Automation Scripts +7 more Show less

DFT Design Verification Python Perl TCL Gate Level Simulation Coverage Analysis Assertions Object-Oriented Programming Logic Design Random Verification Automation Scripts +7 more Show less

DFT Design Verification Gate Level Simulation Python Perl TCL Object-Oriented Programming Coverage Analysis Assertions Logic Design Automation Scripts +6 more Show less

DFT SoC Python Perl TCL Gate Level Simulation Random Verification Coverage Analysis Assertions Logic Design Test Benches Automation Scripts Regressions +8 more Show less

DFT SoC Gate Level Simulation Python Perl TCL Random Verification Coverage Analysis Assertions Verification Plans Test Benches Automation Scripts Logic Design +8 more Show less

SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Debug +10 more Show less

SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Scripting +10 more Show less

SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Scripting +10 more Show less

SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Scripting +10 more Show less

SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Scripting +10 more Show less

SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Scripting +10 more Show less

HPC Cloud Computing Red Hat Linux CentOS OpenStack NVIDIA CUDA TensorFlow SQL Server MySQL Ceph Parallel Programming Containers Data Analysis Project Management +9 more Show less