SoC Full Chip DV Engineer

Apple Inc

Confirmed live today Low trust

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Work type: On-site
Location: Austin, TX
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Similar $197k

$137k $277k

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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TL;DR · SoC Full Chip DV Engineer

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The SoC Full Chip DV Engineer joins the Hardware Technology team to verify the functionality and performance of premier SOCs. This role involves owning the quality of the SOC, IP, or subsystem by reviewing design and architecture specifications while collaborating closely with design and micro-architecture teams. Key responsibilities include developing test plans, coverage plans, and next-generation verification methodologies. The engineer must communicate with software and architecture teams to understand use cases, drive test cases, run regressions, triage bugs, and analyze coverage. Required skills include knowledge of Verilog, SystemVerilog, digital simulation, and debug, along with computer architecture and digital design fundamentals. Preferred experience includes constrained random verification, functional coverage, assertion methodology, UVM, C/C++, assembly, and scripting in Perl or Python to solve complex hardware verification problems.

Skills

SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Scripting

What you'll do

Verify the functionality and performance of Apple’s premier SoCs, IPs, or subsystems.
Review design and architecture specifications to understand functional and performance goals.
Develop comprehensive test plans, test cases, and coverage plans.
Define next-generation verification methodologies and test benches.
Communicate with design, architecture, and software teams to identify use cases and corner conditions.
Run and triage regressions to identify and resolve hardware issues.
Track bugs and analyze coverage metrics to ensure high-quality results.

What we're looking for

Bachelor's degree and at least 10 years of relevant industry experience.
Skilled in digital verification including constrained random verification, functional coverage, code coverage, and assertion methodology (preferred).
Knowledge of Verilog/SystemVerilog, digital simulation, and debug (preferred).
Knowledge of computer architecture and digital design fundamentals (preferred).
Exposure to UVM (preferred).
Experience with C/C++ and assembly (preferred).
Experience with Perl, Python, or similar scripting languages (preferred).
Excellent interpersonal skills and the ability to work independently (preferred).