SoC Full Chip DV Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$150,400–$277,600 / yr
Posted
40 days ago
Freshness
Confirmed live today

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Competitive pay

How this pay compares to similar roles

Similar $197k
This role $214k
$135k $293k
below market most similar roles pay here above market

This role pays more than 63% of similar roles. Most pay $162,000–$231,300 — the blue band above. At the midpoint, this role pays about $214k versus about $197k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · SoC Full Chip DV Engineer

The SoC Full Chip DV Engineer joins the Hardware Technology team to verify the functionality and performance of premier SOCs. This role involves owning the quality of the SOC, IP, or subsystem by reviewing design and architecture specifications and collaborating closely with design and micro-architecture teams. Key responsibilities include developing test plans, coverage plans, and next-generation verification methodologies while defining test benches. The engineer must communicate with software and architecture teams to identify use cases and corner conditions, while also running regressions, triaging bugs, and analyzing coverage. Required skills include knowledge of Verilog, SystemVerilog, digital simulation, and computer architecture. Preferred experience includes constrained random verification, UVM, assertion methodology, C/C++, assembly, and scripting in Perl or Python to solve complex hardware design problems.

What you'll do

  • Verify the functionality and performance of Apple’s premier SoCs, IPs, or subsystems.
  • Review design and architecture specifications to understand functional and performance goals.
  • Develop comprehensive test plans, coverage plans, and next-generation verification methodologies.
  • Build and maintain test benches for digital simulation and debug.
  • Drive test cases by identifying use cases and corner conditions with design and software teams.
  • Run and triage regressions to identify and resolve hardware issues.
  • Track bugs and analyze coverage metrics to ensure high-quality results.

What we're looking for

  • Minimum of a BS degree.
  • Minimum of 3 years of relevant industry experience.
  • Skilled in digital verification including constrained random verification, functional coverage, code coverage, and assertion methodology (preferred).
  • Knowledge of Verilog/SystemVerilog, digital simulation, and debug (preferred).
  • Knowledge of computer architecture and digital design fundamentals (preferred).
  • Exposure to UVM (preferred).
  • Experience with C/C++, assembly (preferred).
  • Experience with perl, python, or similar scripting languages (preferred).

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