SoC Full Chip DV Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $129,300–$194,700 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $198k

This role $162k

$113k $279k

below market most similar roles pay here above market

This role pays less than 75% of similar roles. Most pay $164,313–$231,300 — the blue band above. At the midpoint, this role pays about $162k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · SoC Full Chip DV Engineer

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The SoC Full Chip DV Engineer joins the Hardware Technology team to verify the functionality and performance of premier SOCs. This role involves owning the quality of the SOC, IP, or subsystem by reviewing design and architecture specifications and collaborating with design, micro-architecture, and software teams. Key responsibilities include developing test plans, coverage plans, and next-generation verification methodologies while running regressions, triaging bugs, and analyzing coverage. The position requires expertise in digital verification processes, including constrained random verification, functional coverage, and assertion methodology. Candidates should possess knowledge of Verilog, SystemVerilog, digital simulation, and computer architecture. Preferred skills include UVM, C/C++, assembly, and scripting in Perl or Python. The work focuses on solving complex functional and performance goals within the chip design effort.

Skills

SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Scripting

What you'll do

Verify the functionality and performance of Apple’s premier SoCs, IPs, or subsystems.
Review design and architecture specifications to understand functional and performance goals.
Develop comprehensive test plans, coverage plans, and next-generation verification methodologies.
Build and maintain verification test benches.
Drive test cases by identifying use cases and corner conditions with design and software teams.
Run and triage regressions to identify and resolve hardware issues.
Track bugs and analyze coverage metrics to ensure high-quality results.

What we're looking for

Minimum of a Bachelor of Science degree.
Skilled in digital verification including constrained random verification, functional coverage, code coverage, and assertion methodology (preferred).
Knowledge of Verilog/SystemVerilog, digital simulation, and debug (preferred).
Knowledge of computer architecture and digital design fundamentals (preferred).
Exposure to UVM (preferred).
Experience with C/C++ and assembly (preferred).
Experience with Perl, Python, or similar scripting languages (preferred).
Ability to work independently and possess excellent interpersonal skills (preferred).

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