SoC Full Chip DV Engineer

Apple Inc

Confirmed live today Low trust

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Work type: On-site
Location: Austin, TX
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Similar $197k

$137k $277k

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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TL;DR · SoC Full Chip DV Engineer

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The SoC Full Chip DV Engineer joins the Hardware Technology team to verify the functionality and performance of premier SOCs. In this role, you will own the quality of the SOC, IP, or subsystem by reviewing design and architecture specifications and collaborating closely with design and micro-architecture teams. Your daily responsibilities include developing test plans, coverage plans, and next-generation verification methodologies while defining test benches. You must communicate with software and architecture teams to identify use cases and corner conditions. Key tasks involve running and triaging regressions, tracking bugs, and analyzing coverage. Required skills include Verilog, SystemVerilog, digital simulation, and debug. Preferred experience includes constrained random verification, functional coverage, assertion methodology, UVM, C/C++, assembly, and scripting in Perl or Python.

Skills

SystemVerilog Verilog UVM Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Python Perl C++ Assembly Digital Simulation Computer Architecture Digital Design Scripting

What you'll do

Verify the functionality and performance of Apple’s premier SoCs, IPs, or subsystems.
Review design and architecture specifications to understand functional and performance goals.
Develop comprehensive test plans, coverage plans, and verification methodologies.
Build and maintain test benches for digital simulation and debug.
Identify and drive test cases based on use cases and corner conditions.
Run and triage regressions to identify and track hardware bugs.
Analyze coverage metrics to ensure all design requirements are met.

What we're looking for

Bachelor's degree and a minimum of 3 years of relevant industry experience.
Skilled in digital verification including constrained random verification, functional coverage, code coverage, and assertion methodology (preferred).
Knowledge of Verilog/SystemVerilog, digital simulation, and debug (preferred).
Knowledge of computer architecture and digital design fundamentals (preferred).
Exposure to UVM (preferred).
Experience with C/C++ and assembly (preferred).
Experience with Perl, Python, or similar scripting languages (preferred).
Ability to work independently and possess excellent interpersonal skills (preferred).