Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: SOC Design Verification Engineer Remove filter Clear all

20 of up to 20 (filtered)

SOC Design Verification Engineer

Apple Inc

Sunnyvale, CA 11 days ago $129,300–$225,300
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog UVM Verilog UPF Python C C++ Formal Verification JasperGold PCIe AXI AHB SVA ASIC SOC Perl Assembly
Save

SOC Design Verification Engineer

Apple Inc

San Diego, CA 11 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Below market
SystemVerilog UVM Verilog UPF Python C C++ Formal Verification JasperGold PCIe AXI AHB SVA RTL ASIC SOC WiFi Bluetooth Perl
Save

SOC Design Verification Engineer

Apple Inc

Irvine, CA 11 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Below market
SystemVerilog UVM Verilog UPF Python C++ Perl Formal Verification JasperGold SVA PCIe AXI AHB WiFi Bluetooth RTL Verification AI/ML
Save

SOC Design Verification Engineer

Apple Inc

Sunnyvale, CA 11 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM Verilog UPF Python C C++ Formal Verification JasperGold PCIe AXI AHB SVA Perl RTL ASIC SOC WiFi Bluetooth
10+ yrs exp
Save

SOC Design Verification Engineer

Apple Inc

San Diego, CA 11 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM Verilog UPF Python C++ Perl Formal Verification JasperGold SVA PCIe AXI AHB WiFi Bluetooth RTL Verification AI/ML Assembly
10+ yrs exp
Save

SOC Design Verification Engineer

Apple Inc

Irvine, CA 11 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM Verilog UPF Python C++ Perl Formal Verification JasperGold SVA ASIC SOC PCIe AXI AHB WiFi Bluetooth AI/ML
10+ yrs exp
Save

SOC Design Verification Engineer

Qualcomm

San Diego, CA 20 days ago $101,400–$152,200
Actively hiring Confirmed live today Trusted Below market
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design
Save

SOC Design Verification Engineer

Qualcomm

San Diego, CA 21 days ago $121,800–$182,600
Actively hiring Confirmed live today Trusted Below market
System Verilog UVM C Assertion-Based Verification (SVA) Coverage-Driven Verification Python Formal Verification Portable Stimulus (PSS) PCIe CXL DDR HBM Ethernet Veloce Palladium ZeBu RTL SoC Architecture AI/ML Accelerators
2+ yrs exp
Save

SOC Design Verification Engineer

Qualcomm

San Diego, CA 25 days ago $101,400–$152,200
Actively hiring Confirmed live yesterday Trusted Below market
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting
Save

GSoC Design Verification Engineer

Qualcomm

San Diego, CA 34 days ago $101,400–$152,200
Actively hiring Confirmed live today High trust Below market
System Verilog UVM C Assertion-Based Verification (SVA) Python Coverage-Driven Verification RTL Formal Verification Portable Stimulus (PSS) LLM RAG PCIe Ethernet DDR HBM Veloce Palladium ZeBu Cache Coherency ACE CHI CXL
Save

SOC Design Verification Engineer-Staff

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting SoC
4+ yrs exp
Save

SOC Design Verification Engineer

Qualcomm

San Diego, CA 40 days ago $121,800–$182,600
Actively hiring Confirmed live today Trusted Below market
System Verilog UVM C Assertion-Based Verification (SVA) Coverage-Driven Verification Python Portable Stimulus (PSS) Formal Verification PCIe CXL DDR HBM Ethernet Veloce Palladium ZeBu RTL SoC Architecture AI/ML Accelerators
2+ yrs exp
Save

SOC Design Verification Engineer

Qualcomm

San Diego, CA 40 days ago $101,400–$152,200
Actively hiring Confirmed live yesterday Low trust Below market
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design
Save

SOC Design Verification Engineer-Staff

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting SoC IC Package
4+ yrs exp
Save

SOC Design Verification Engineer-Staff

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting SoC
4+ yrs exp
Save

SoC Physical Design Verification Engineer

Apple Inc

San Jose, CA 90 days ago $184,700–$324,800
Actively hiring Confirmed live today Low trust Above market
LVS DRC ANT HVDRC Physical Verification Python Perl Tcl Mentor Calibre Synopsys ICV Layout Design Tapeout Design-for-Manufacturing Design-for-Yield Lithography RDL Design
10+ yrs exp
Save

SoC Physical Design Verification Engineer

Apple Inc

Beaverton, OR 90 days ago
Actively hiring Confirmed live yesterday Low trust
LVS DRC ANT HVDRC Physical Verification Python Perl Tcl Mentor Calibre Synopsys ICV Tapeout Layout Design Design-for-Manufacturing Design-for-Yield Lithography RDL ESD
10+ yrs exp
Save

SoC Physical Design Verification Engineer

Apple Inc

Austin, TX 90 days ago
Actively hiring Confirmed live today Low trust
LVS DRC ANT HVDRC ASIC Physical Design Physical Verification Mentor Calibre Synopsys ICV Python Perl Tcl Tapeout Layout Design Design-for-Manufacturing Design-for-Yield Lithography RDL ESD Mixed Signal Back-end Verification
10+ yrs exp
Save

SoC Design Verification Engineer

Amd

San Jose, CA 90 days ago $141,760–$212,640
Actively hiring Confirmed live today Trusted Below market
System Verilog Verilog UVM C++ C Python Perl SOC Architecture Computer Architecture AXI AHB PCIe DDR Functional Verification Performance Verification Code Coverage Functional Coverage
Save

SoC Physical Design Verification Engineer

Apple Inc

Beaverton, OR 126 days ago
Actively hiring Confirmed live today Low trust
LVS DRC ANT HVDRC ASIC Physical Design Physical Verification Mentor Calibre Synopsys ICV Python Perl Tcl Tapeout Layout Design Design-for-Manufacturing Design-for-Yield Lithography RDL ESD Mixed Signal Back-end Verification
3+ yrs exp
Save