SOC Design Verification Engineer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$101,400–$152,200 / yr
Posted
25 days ago
Freshness
Confirmed live yesterday
Closes
Mar 31, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $127k
$86k $248k
below market most similar roles pay here above market

This role pays less than 98% of similar roles. Most pay $168,500–$230,087 — the blue band above. At the midpoint, this role pays about $127k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 589 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 563 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · SOC Design Verification Engineer

Role Posting Log in to save

The SOC Design Verification Engineer joins the ASICS Engineering group to support the development of high performance, high quality, and low power products. This role involves defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP development for blocks and SoCs. Day-to-day responsibilities include creating architectures, circuit specifications, logic designs, and system simulations based on system-level requirements. The engineer will collaborate on implementation strategies, evaluate process flows from high-level design to synthesis, place and route, and timing and power use, and write technical documentation for projects. Required skills include experience with architecture and design tools, scripting tools, programming languages, and design verification methods. The role specifically utilizes tools such as Virtuoso and RTL to GDS Flow to enable the design of specific IC packages.

Skills

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting

What you'll do

  • Define, model, design, and optimize IP block and SoC development for high-performance products.
  • Verify, validate, and document the implementation of digital and analog designs.
  • Create architectures, circuit specifications, logic designs, and system simulations based on requirements.
  • Develop implementation strategies that align with system requirements and customer needs.
  • Evaluate process flows from high-level design through synthesis, place and route, and timing.
  • Use tools like RTL to GDS Flow and Virtuoso to execute architecture and design tasks.
  • Write technical documentation for EDA, IP, and ASIC projects.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field.
  • Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science (preferred).
  • 6+ months of experience with architecture and design tools (preferred).
  • 6+ months of experience with scripting tools and programming languages (preferred).
  • 6+ months of experience with design verification methods (preferred).

Related searches

More SOC Design Verification Engineer jobs SOC Design Verification Engineer jobs in San Diego All jobs at Qualcomm

More like this

Similar roles

SOC Design Verification Engineer

Qualcomm

San Diego, CA 20 days ago $101,400–$152,200
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design
Save

SOC Design Verification Engineer-Staff

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting SoC
4+ yrs exp
Save

SOC Design Verification Engineer

Qualcomm

San Diego, CA 40 days ago $101,400–$152,200
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design
Save

DFT Engineer

Qualcomm

San Diego, CA 18 days ago $101,400–$152,200
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting
Save