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Physical Design Netlist to GDSII Floorplanning Design Partitioning Block Pin Assignment PnR Timing Closure Physical Verification IR/EM Analysis Tcl Perl Python Low-power IC Design +8 more Show less

Verilog VHDL Python Perl C RTL Synthesis STA CDC Lint HDL ASIC DSP High-level Synthesis Unix Digital Signal Processing Error Correction Code Design for Test Design for Manufacturing +14 more Show less

RTL Design Python Perl Ethernet IP Switching Front End Design AI/ML +2 more Show less

SystemVerilog UVM Verilog C++ C ASIC Verification FPGA Ethernet PCIe Networking Protocols Object-Oriented Programming ASIC Design Flow +7 more Show less

ASIC Design RTL Synthesis Verilog TCL Perl Synopsys Design Compiler Cadence RTL Compiler Formal Verification Synopsys Formality Cadence Conformal Spyglass Lint DFT Scan Methodology Git SVN Timing Analysis Power Analysis +12 more Show less

C++ VLSI Physical Design Machine Learning Python Perl Tcl ICC2 Innovus PrimeTime Tempus StarRC Distributed Computing Multithreading Reinforcement Learning GNNs EDA Tools +11 more Show less

C++ VLSI Physical Design Machine Learning Python Perl Tcl ICC2 Innovus PrimeTime Tempus StarRC Distributed Computing Multithreading Reinforcement Learning Graph Neural Networks Parallel Computing EDA Tools +13 more Show less

ASIC Design RTL Synthesis Verilog TCL Perl Synopsys Design Compiler Cadence RTL Compiler Formal Verification Synopsys Formality Cadence Conformal Spyglass Lint DFT Scan Methodology Git SVN Timing Analysis Power Analysis +12 more Show less

C++ VLSI Physical Design Computational Geometry Graph Theory Placement Routing Floorplanning Machine Learning Multithreading Distributed Computing ICC2 Innovus CAD EDA Visualization C++17 C++14 +12 more Show less

CoWoS 2.5D 3D Integration Cadence Innovus Synopsys 3DIC Compiler Mentor Graphics (Calibre Python Tcl SKILL TSV Design Signal Integrity Power Integrity Thermal Analysis 3DBlox Semiconductor Fabrication EDA Tools Physical Verification +12 more Show less

SystemVerilog UVM C RTL ATE Design Verification Testbenches Checkers Transactors Networking Switching Gatesim +7 more Show less

SystemVerilog UVM C RTL GateSim ATE Design Verification Testbenches Checkers Transactors Networking Switching +7 more Show less