Software R&D Engineer, VLSI Physical Design

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TXSanta Clara, CA
Salary
$116,000–$189,750 / yr
Posted
51 days ago
Freshness
Confirmed live yesterday

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $181k
This role $153k
$104k most similar roles pay here $229k

This role pays less than 65% of similar roles. Most pay $146,245–$216,250 — the shaded band above. At the midpoint, this role pays about $153k versus about $181k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Software R&D Engineer, VLSI Physical Design

Software R&D Engineer, VLSI Physical Design - New College Grad 2026 will join a team developing internal EDA tools by fusing parallel computing, machine learning, and specialized algorithms for VLSI design. The role involves inventing new optimization engines to fuse independent processes like legalization and sizing to increase chip frequency while minimizing power consumption. You will improve C++ algorithms for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction. Required skills include proficiency in C++, Perl, Tcl, and Python, alongside knowledge of tools like ICC2, Innovus, PrimeTime, Tempus, and StarRC. The work focuses on solving complex physical design challenges including timing optimization, interconnect models, crosstalk, IR drop, and congestion to improve PPA across advanced hardware designs while navigating the intersection of software and hardware engineering.

What you'll do

  • Invent new optimization engines that fuse independent processes like legalization and sizing to improve chip frequency and power.
  • Develop and optimize C++ algorithms for gate-level sizing, buffering, clock skew, and cell legalization.
  • Improve software for power minimization, ECO routing, and incremental parasitic extraction.
  • Design high-performance software utilizing multithreading, distributed computing, and efficient memory management.
  • Integrate machine learning frameworks, such as GNNs or reinforcement learning, into physical design workflows.
  • Manage the full lifecycle of optimization from initial discovery and invention to final deployment in design teams.

What we're looking for

  • Master's or PhD degree in Electrical Engineering or Computer Science (or equivalent experience).
  • Experience in VLSI algorithm development using C++.
  • Understanding of VLSI timing optimization and related concepts like cell libraries, interconnect models, and IR drop.
  • Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC.
  • Proficiency in scripting languages including Perl, Tcl, and Python.
  • Experience with C++14 or newer features, including lambdas and concurrency.
  • Experience in high-performance software design involving multithreading, distributed computing, and efficient memory/IO use.
  • Experience with machine learning frameworks such as reinforcement learning and Graph Neural Networks (GNNs).

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