below marketmost similar roles pay hereabove market
This role pays less than
67%
of similar roles. Most pay
$147,200–$216,250
— the blue band above.
At the midpoint, this role pays about
$153k
versus about
$182k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
1623 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 1110 roles with salary data.
JOB TITLE: Software R&D Engineer, VLSI Physical Design - New College Grad 2026
The Software R&D Engineer, VLSI Physical Design - New College Grad 2026 joins a team developing internal EDA tools by fusing parallel computing, machine learning, and specialized algorithms. You will invent new optimization engines that fuse independent processes like legalization and sizing to increase chip frequency while minimizing power consumption. Daily responsibilities include improving C++ algorithms for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction. The role requires expertise in VLSI timing optimization, cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, and congestion. Candidates should be familiar with ICC2, Innovus, PrimeTime, Tempus, and StarRC, along with Perl, Tcl, and Python. You will solve complex physical design problems to improve PPA for advanced AI hardware.
Invent new optimization engines that fuse independent processes like legalization and sizing.
Improve C++ algorithms for gate-level sizing, buffering, and cell legalization.
Develop software for useful clock skew, power minimization, and ECO routing.
Optimize incremental parasitic extraction and other VLSI physical design algorithms.
Own the full process from discovering new optimization opportunities to developing solutions.
Work directly with design teams to facilitate the deployment of new software tools.
Focus on increasing chip frequency while minimizing power consumption across internal tools.
What we're looking for
Masters or PhD in Electrical Engineering or Computer Science (or equivalent experience).
Experience with VLSI algorithms development using C++.
Understanding of VLSI timing optimization and concepts including cell libraries, interconnect models, crosstalk, glitches, IR drop, and timing constraints.
Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC.
Familiarity with design flows written in Perl, Tcl, and Python.
C++14 or newer experience, such as lambdas and concurrency (preferred).
Experience in high performance software design including multithreading, distributed computing, and efficient memory and I/O use (preferred).
Experience with reinforcement learning, GNNs, and other machine learning frameworks applied to physical design (preferred).
Remote (Santa Clara, CA)+15 days ago
$168,000–$264,500
Physical Design
EDA Tools
PPA
TCL
Python
C++
Perl
Cadence
Innovus
Genus
Tempus
Quantus
Joules
STA
UPF
FSDB
SAIF
PyTorch
NumPy
SciPy
scikit-learn
ML
AI
Synthesis
DFT