Software R&D Engineer, VLSI Physical Design - New College Grad 2026

Nvidia

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$116,000–$189,750 / yr
Posted
2 days ago

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $185k
This role $153k
$104k most similar roles pay here $231k

This role pays less than 75% of similar roles. Most pay $153,100–$216,250 — the shaded band above. At the midpoint, this role pays about $153k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Software R&D Engineer, VLSI Physical Design - New College Grad 2026

As a R&D Software Engineer at NVIDIA, you will join a cutting-edge team focused on developing highly optimized EDA tools for VLSI design by integrating advances in parallel computing and machine learning. Your primary responsibilities include inventing new optimization engines that co-optimize traditionally independent processes to enhance chip frequency while reducing power consumption. You will also refine algorithms for gate-level sizing, buffering, clock skew management, cell legalization, and incremental parasitic extraction using C++. The role requires a deep understanding of VLSI timing optimization concepts and proficiency with design implementation tools like ICC2, Innovus, PrimeTime, Tempus, and StarRC. Ideal candidates hold a Masters or PhD in Electrical Engineering or Computer Science and have experience with C++14 or newer, reinforcement learning, GNNs, and continuous software improvement for PPA (power-performance-area) optimization.

What you'll do

  • Invent new optimization engines that integrate multiple independent processes for better chip performance.
  • Enhance algorithms for gate-level sizing, buffering, clock skew management, legalization, power minimization, ECO routing, and parasitic extraction.
  • Develop solutions from discovery to deployment, working closely with design teams to implement innovations.
  • Utilize C++14 or newer features to create efficient and concurrent software for VLSI optimization tools.
  • Apply machine learning frameworks like reinforcement learning and GNNs to improve physical design processes.
  • Continuously refine software to optimize power, performance, and area (PPA) in chip designs.

What we're looking for

  • Masters or PhD in Electrical Engineering or Computer Science.
  • Proven experience developing VLSI algorithms using C++.
  • Deep understanding of VLSI timing optimization concepts.
  • Familiarity with design implementation tools like ICC2, Innovus, PrimeTime.
  • Experience with modern C++ features including lambdas and concurrency.
  • Knowledge of how to fuse Physical Design steps for better PPA.
  • Expertise in reinforcement learning and Graph Neural Networks applied to physical design.

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