Physical Design Engineer

Broadcom

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$120,000–$192,000 / yr
Posted
40 days ago
Closes
Oct 24, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $169k
This role $156k
$110k most similar roles pay here $212k

This role pays less than 62% of similar roles. Most pay $139,000–$199,650 — the shaded band above. At the midpoint, this role pays about $156k versus about $169k for comparable roles.

Based on 239 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Physical Design Engineer

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Broadcom seeks a senior-level ASIC top level floorplan Physical Design Engineer to join its Asic Products Division, focusing on cutting-edge AI and PCIe Switch Products. This role entails owning chip floor planning, partition creation, clock tree delivery, and resolving physical design issues related to integration and assembly. The engineer will manage cross-functional interactions with the package team for top-level floorplanning, I/O, and bump planning while developing methodologies using industry tools. Preferred candidates have extensive experience in die size estimation, partitioning, clocking, pin assignment, and advanced node tape-out, along with expertise in scripting languages like Python or Tcl. The ideal candidate will collaborate closely with design, package, and methodology teams and must work on-site at the San Jose location.

Skills

Python Tcl Perl Hierarchical_design_planning Power_grid_design Structured_clocks Top_level_pipeline_placement Custom_routes Bump_planning RDL_routes Multi_voltage_domain_designs DRC LVS EMIR Chiplet SerDes HBM DDR Switch_Fabric Arbiter

What you'll do

  • Own chip floor planning, partition creation, and clock tree delivery.
  • Resolve physical design issues related to chip integration and assembly.
  • Manage cross-functional interactions with the package team for top level floorplanning.
  • Develop and improve floorplan methodologies using industry and internal tools.
  • Perform technical evaluations of IPs, providing recommendations to meet specifications.

What we're looking for

  • 8+ years of experience in ASIC top level floorplanning with a focus on die size estimate, partitioning, clocking, and pin assignment.
  • Experience working on various technologies including Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, chiplet designs.
  • Proven ability to resolve advanced node chip-level DRC/LVS/EMIR issues and manage tape-out processes.
  • Strong background in bump planning, RDL routes, multi-voltage domain designs, hierarchical design planning, power grid design, and structured clocks.
  • Extensive experience collaborating with cross-functional teams including design, package, and methodology during development phases.
  • Proficiency in scripting languages such as Python, Tcl, or Perl for automation and tool development.

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