Physical Design Engineer

Broadcom

Closes in 3 days

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $141,300–$226,000 / yr
Posted: 108 days ago
Closes: Jun 9, 2026 (soon)

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $169k

This role $184k

$117k most similar roles pay here $238k

This role pays more than 69% of similar roles. Most pay $139,000–$199,650 — the shaded band above. At the midpoint, this role pays about $184k versus about $169k for comparable roles.

Based on 239 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Physical Design Engineer

Apply Now Log in to save

Broadcom is seeking a senior ASIC top level floorplan Physical Design Engineer to join its Asic Products Division, focusing on cutting-edge AI and PCIe Switch Products. This role entails owning chip floor planning, partition creation, clock tree delivery, and resolving physical design issues related to integration and assembly. The engineer will develop methodologies using industry-standard tools, evaluate IPs for technical fit, and collaborate closely with cross-functional teams including package engineering. Ideal candidates have extensive experience in die size estimation, partitioning, and multi-voltage domain designs, along with expertise in scripting languages like Python or Tcl. They should possess a strong background in hierarchical design planning, power grid design, and tape-out processes for advanced nodes, ensuring successful silicon tapeout of complex AI and switch products.

Skills

Python Tcl Perl DV DRC LVS EMIR bump_planning RDL_routes multi_voltage_domain_design hierarchical_design_planning power_grid_design structured_clocks top_level_pipeline_placement custom_routes package_team_collaboration design_teams_collaboration methodology_teams_collaboration

What you'll do

Own chip floor planning, partition creation, and clock tree delivery.
Resolve physical design issues related to chip integration and assembly.
Manage cross-functional interactions with the package team for top level floorplanning.
Develop and improve floorplan methodologies using industry and internal tools.
Perform technical evaluations of IPs, providing recommendations to meet specifications.

What we're looking for

12+ years of experience in top-level floorplanning with a focus on die size estimate, partitioning, clocking, and pin assignment.
Experience working on various technologies including Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, and chiplet designs.
Proven ability to resolve chip level DRC/LVS/EMIR issues for advanced nodes and tape out experience.
Strong background in bump planning, RDL routes, and multi-voltage domain designs.
Experience with hierarchical design planning, power grid design, structured clocks, top-level pipeline placement, custom routes, and bump planning.
Proficiency in scripting languages such as Python, Tcl, or Perl for automation tasks.

Similar roles

Physical Design Engineer

Broadcom

San Jose, CA 40 days ago $120,000–$192,000

Python Tcl Perl Hierarchical_design_planning Power_grid_design Structured_clocks Top_level_pipeline_placement Custom_routes Bump_planning RDL_routes Multi_voltage_domain_designs DRC LVS EMIR Chiplet SerDes HBM DDR Switch_Fabric Arbiter

Save

Design Engineer

Broadcom

Fort Collins, CO 101 days ago $60,200–$96,300

UNIX Linux TCL Python Perl Cadence_Innovus Synopsys_ICC2 PrimeTime VLSI CMOS_logic digital_circuit_fundamentals floorplanning placement routing timing_closure physical_verification DRC LVS block_level_integration EDA_tools

Save

Hardware Board Design Engineer

Qualcomm

Santa Clara, CA 30 days ago $180,500–$270,700

OrCAD Cadence Allegro PCIe DDR Ethernet SerDes SIPI PDN EMI Python TCL Perl Oscilloscopes Logic analyzers Protocol analyzers High-speed design High-power design MULTILAYER PCBs Cross-functional collaboration Technical documentation

Save

Physical Design Engineer

Qualcomm

San Diego, CA 41 days ago $98,500–$147,700

Virtuoso RTL to GDS Flow Verilog SystemVerilog Python Perl TCL UVM DVFlow PrimeTime PTPX ICC Calibre Sonata QCAT Qualcomm SNAP Linux Git JIRA Confluence

Save

Staff, Physical Design Engineer

Qualcomm

Santa Clara, CA 100 days ago $153,200–$229,800

Virtuoso RTL to GDS Flow Verilog SystemVerilog Python Perl TCL UVM DVFlow PrimeTime PT PowerAware ICC/Innovus Calibre Synopsys DC Cadence Genus ModelSim/QuestaSim Linux Git JIRA Confluence

Save

Design Engineer

Ramp

Remote (New York City, New York, US) 117 days ago $172,000–$440,000

React TypeScript JavaScript HTML CSS Cursor Claude Code Figma LLMs Performance Accessibility Core Web Vitals Semantic HTML Modern CSS Design Systems Reusable Components Self-Serve Research Tools Interactive Prototypes High Visual Craft Interaction Craft

Remote

Save