CPU Server Physical Design Timing Engineer

Qualcomm

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$198,700–$298,100 / yr
Posted
97 days ago
Closes
Aug 26, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k
This role $248k
$135k most similar roles pay here $316k

This role pays more than 89% of similar roles. Most pay $156,900–$225,525 — the shaded band above. At the midpoint, this role pays about $248k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 615 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 556 roles with salary data.

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At a glance

TL;DR · CPU Server Physical Design Timing Engineer

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As a CPU Physical Design Timing Engineer at Qualcomm Technologies, Inc., you will join the NUVIA team to drive timing closure for Oryon CPU cores, collaborating closely with microarchitecture and RTL design teams to ensure aggressive power, area, and performance goals are met. Your day-to-day responsibilities include setting up STA constraints, conducting timing analysis across various conditions using tools like PT/Tempus, and developing automation scripts within STA/PD tools to enhance methodology. You will also work on cross-collaborative projects with Qualcomm’s central timing technology team and the CPU implementation team to optimize PPA goals. Essential skills for this role include expertise in STA timing analysis, AOCV/POCV concepts, CTS, and scripting languages such as TCL, Perl, Python, alongside familiarity with digital flow design tools like ICC2 and Innovus.

Skills

TCL Perl Python Prime-time Tempus ICC2 Innovus STA AOCV POCV CTS ASIC Cross-talk noise Signal Integrity Layout Parasitic Extraction

What you'll do

  • Define and develop timing constraints for Oryon CPU Cores.
  • Conduct timing analysis and validation across various PVT conditions using PT/Tempus.
  • Optimize STA flow and correlate Spice to STA results.
  • Debug root causes of timing miscorrelation at different design levels.
  • Evaluate and implement new timing methodologies on diverse technology nodes.
  • Develop automation scripts within STA/PD tools for methodology advancement.

What we're looking for

  • Extensive experience in STA timing analysis and managing timing constraints.
  • Proficiency in Prime-time and Tempus tools for STA flow optimization.
  • Hands-on experience with digital design implementation from RTL to GDS using ICC2, Innovus.
  • Strong scripting skills in TCL, Perl, and Python for automation and methodology development.
  • Expertise in cross-talk noise, signal integrity, and layout parasitic extraction.
  • Ability to drive timing convergence at chip-level and hard-macro level designs.
  • In-depth knowledge of ASIC back-end design flows and methods.

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