Physical Design Engineer II, Silicon Engineering

SpaceX

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Austin, TX
Posted
133 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $187k
$141k most similar roles pay here $240k

This listing doesn't post a salary. Most similar roles pay $155,000–$219,043.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer II, Silicon Engineering

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Physical Design Engineer II (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. The role involves performing partition synthesis and physical implementation steps, including floorplanning, power/ground grid generation, place and route, and various signoff checks such as timing, noise, electromigration, and voltage drop. You will also develop automation scripts, conduct architectural feasibility studies with the ASIC design team, and resolve complex congestion or flow issues. Required skills include experience in RTL2GDSII physical design, knowledge of deep sub-micron FinFET and CMOS solid state physics, and proficiency in scripting languages like Python, Perl, TCL, and Bash. The work focuses on solving connectivity challenges by building high-performance chips to expand the capabilities of a global satellite network for reliable internet access in remote areas.

Skills

ASIC Physical Design RTL2GDSII Static Timing Analysis STA EDA Tools Python TCL Perl Bash Makefile FinFET CMOS DFT Scan MBIST LBIST Floorplanning Place and Route Synthesis

What you'll do

  • Perform partition synthesis and physical implementation steps including floorplanning, power/ground grid generation, and place and route.
  • Execute signoff checks for timing, noise, physical verification, electromigration, and voltage drop.
  • Develop and improve physical design methodologies and automation scripts for various implementation steps.
  • Conduct architectural feasibility studies to establish timing, power, and area design targets.
  • Resolve complex design, timing, and congestion issues while identifying and driving technical solutions.
  • Debug and fix signoff closure issues in static timing analysis and logic equivalency.
  • Explore RTL and design tradeoffs to optimize ASIC performance for space and ground infrastructure.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 3+ years of professional experience in RTL2GDSII physical design and/or physical design flow development.
  • Experience with industry standard EDA tools and understanding of their capabilities and algorithms.
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics.
  • Understanding of CMOS digital design principles, standard cell functionality, and power dissipation in deep submicron processes.
  • Familiarity with CMOS analog circuit and physical design.
  • Basic knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows.
  • Proficiency in scripting languages such as csh, bash, Perl, Python, TCL, or Makefile.
  • Ability to meet ITAR requirements regarding U.S. citizenship, permanent residency, or other eligible status.

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